analog_case_item ::=

analog_expression { , analog_expression } : analog_statement_or_null | default [ : ] analog_statement_or_null

Syntax 5-9—Syntax for case statement

The default statement is optional. Use of multiple default statements in one case statement is illegal.

The analog_expression and the analog_case_item expression can be computed at runtime; neither expression is required to be a constant expression.

The analog_case_item expressions are evaluated and compared in the exact order in which they are given. During this linear search, if one of the analog_case_item expressions matches the analog_expression given in parentheses, then the statement associated with that analog_case_item is executed. If all comparisons fail, and the default item is given, then the default item statement is executed; otherwise none of the analog_case_item statements are executed.

The casex and the casez versions of the case statement are described in 7.3.2 and IEEE std 1364-2005 Verilog HDL.

5.8.4 Restrictions on conditional statements

Since analog filter functions have to be evaluated at every time point these are restricted to be used inside conditional statements (if-else-if and case) unless the conditional expression is a constant expression. Also, for the use of analog filter functions, the conditional statements cannot be conditionally executed (nested conditional statements). Contributions statements are allowed as part of the conditional analog statements (refer 5.6.5 for details on switch branches).

Event control statements (e.g.: timer, cross) cannot be used inside conditional statements unless the conditional expression is a constant expression.

5.9 Looping statements

There are several types of looping statements: repeat, while, and for. These statements provide a means of controlling the execution of a statement zero (0), one (1), or more times.

The for looping statements can be used to describe analog behaviors using analog operators.

The following restrictions are applied to looping statements (repeat, while and for) except for analog_for statements, refer 5.9.3

—Analog filter functions are not allowed

—Event control statements are not allowed

—Contribution statements are not allowed

5.9.1 Repeat and while statements

repeat() executes a statement a fixed number of times. Evaluation of the expression decides how many times a statement is executed.

while() executes a statement until an expression becomes False. If the expression starts out False, the statement is not executed at all.

The repeat and while expressions shall be evaluated once before the execution of any statement in order to determine the number of times, if any, the statements are executed. The syntax for repeat() and while() statements is shown in Syntax 5-10.

5.9.2 For statements

The for() statement is a looping construct which controls execution of its associated statement(s) using an index variable. In the case of analog_for statement the control mechanism shall consist of genvar_initialization and genvar_expressions to adhere to the restrictions associated with the use of analog operators. Syntax 5-11 shows the syntax for the looping statements that can be used in analog behavior.

analog_loop_statement ::= // from A.6.8

...

| for ( analog_variable_assignment ; analog_expression ; analog_variable_assignment ) analog_statement

Syntax 5-11—Syntax for the for statements

The for() statement controls execution of its associated statement(s) by a three-step process:

1)it executes an assignment normally used to initialize an integer which controls the number of loops executed.

2)it evaluates an expression—if the result is zero (0), the for-loop exits; otherwise, the for-loop executes its associated statement(s) and then performs Step 3.

3)it executes an assignment normally used to modify the value of the loop-control variable and repeats Step 2.

5.9.3 Analog For Statements

The analog_for statements are syntactically equivalent to for() statements except the associated analog statement can contain analog operators. The analog_loop_generate_statement puts the additional restriction upon the procedural assignment and conditional expressions of the for-loop to be statically evaluatable. Ver- ilog-AMS HDL provides genvar-derived expressions for this purpose. Syntax 5-12 shows the syntax for the analog_for statement.