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Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

For example, suppose a module named nmos2 has the following declarations in the module:

parameter real dtemp = 0 from [-‘P_CELSIUS0:inf); aliasparam trise = dtemp;

Then the following two instantiations of the module are valid:

nmos2 #(.trise(5)) m1(.d(d), .g(g), .s(s), .b(b)); nmos2 #(.dtemp(5)) m2(.d(d), .g(g), .s(s), .b(b));

and the value of the parameter dtemp, as used in the module equations for both instances, is 5.

This last instantiation is an error:

nmos2 #(.trise(5), .dtemp(5)) m3(.d(d), .g(g), .s(s), .b(b)); //error

because an override is specified for the parameter dtemp and its alias, even though the values are equal.

3.5 Genvars

Genvars are integer-valued variables which compose static expressions for instantiating structure behaviorally such as accessing analog signals within behavioral looping constructs. The syntax for declaring genvar variables is shown in Syntax 3-3.

genvar_declaration ::=

// from A.4.2

genvar list_of_genvar_identifiers ;

 

list_of_genvar_identifiers ::=

 

genvar_identifier { , genvar_identifier }

 

Syntax 3-3—Syntax for genvar declaration

The static nature of genvar variables is derived from the limitations upon the contexts in which their values can be assigned.

Examples:

genvar i; analog begin

...

for (i = 0; i < 8; i = i + 1) begin V(out[i]) <+ transition(value[i], td, tr);

end

...

end

The genvar variable i can only be assigned within the for-loop control. Assignments to the genvar variable i can consist only of expressions of static values, e.g., parameters, literals, and other genvar variables.

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