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Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

a scalar member of a vector net or port declared within the module

a sub-range of a vector net or port declared within the module

a vector net formed as a result of the concatenation operator

The port expression is optional so the instantiating module can document the existence of the port without connecting it to anything. The parentheses are required.

The two types of module port connections can not be mixed; connections to the ports of a particular module instance shall be all by order or all by name.

Examples:

module adc4 (out, rem, in);

input in;

output rem;

output [3:0] out;

electrical [3:0] out; electrical in, rem, rem_chain;

adc2 hi (.in(in), .out(out[3:2]), .remainder(rem_chain)); adc2 lo (.in(rem_chain), .out(out[1:0]), .remainder(rem));

endmodule

module adc2 (out, in, remainder);

output [1:0] out;

output remainder;

input in;

 

electrical [1:0] out; electrical in, remainder, r;

// adc is same as defined in 6.5.4 adc hi1 (out[1], r, in);

adc lo1 (out[0], remainder, r); endmodule

Since these connections were made by port name, the order in which the connections appear is irrelevant.

6.5.6 Detecting port connections

When a module is instantiated, all of its ports need not be connected. For example, a clock module may provide outputs clk and clkbar, but a design may only need clk. In some cases, it may be important to know whether a particular port is connected. For example, if the transition() filter of 4.5.8 is used on the outputs, it might speed up the simulation if the filter is only used when the port is connected. The $port_connected() function described in 9.19 can be used to determine whether a port is connected.

6.5.7 Port connection rules

All digital ports connected to a net shall be of compatible disciplines, as shall all analog ports connected to a net. Ports of both analog and digital discipline may be connected to a net provided the appropriate connect statements exist (see 7.7).

6.5.7.1 Matching size rule

A scalar port can be connected to a scalar net and a vector port can be connected to a vector net or concatenated net expression of the matching width. In other words, the sizes of the ports and net need to match.

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