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Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

5.6.7.2 Indirect and direct contribution

Indirect contribution statements is incompatible with direct contribution statements across the same pair of analog nets (or any of its parallel branches). Once a value is indirectly assigned to a branch, it cannot be contributed to using the branch contribution operator <+.

5.7 Analog procedural assignments

Analog procedural assignments are used for modifying analog integer and real variables. The syntax for procedural assignments shown in Syntax 5-7.

analog_procedural_assignment ::= analog_variable_assignment ;

// from A.6.2

analog_variable_assignment ::= analog_variable_lvalue = analog_expression

// from A.8.5

analog_variable_lvalue ::=

variable_identifier

 

| variable_identifier [ analog_expression ] { [ analog_expression ] }

 

 

 

Syntax 5-7—Syntax for procedural assignments

 

The left-hand side of a procedural assignment shall be an integer or real identifier or an element of an integer or real array. The right-hand side expression can be any arbitrary expression constituted from legal operands and operators as described in Clause 4.

An analog_procedural_assignment is defined is a variable assignment whose right-hand side expression is an analog_expression involving analog operators. The following semantic restrictions are applicable to the analog_expression in the analog_procedural_assignment syntax:

Concatenation expressions cannot be used as part of the analog_expression (assigning to list of values in the analog context is not allowed).

Analog filter functions cannot be used as part of the analog_expression syntax if the statement is conditionally executed during simulation.

Hierarchical assignment of a variable from another scope/module is not allowed

5.8Analog conditional statements

There are two types of conditional statement allowed in analog behavior:

if-else-if statements

case statements

5.8.1 if-else-if statement

The if-else statement is used to determine whether a statement is executed or not. The syntax of a analog conditional statement is shown in Syntax 5-8. If any of the conditionally-executed statements (analog_statement_or_null) contains an analog operator, the conditional expression (analog_expression) shall be a analysis_or_constant_expression. (See the discussion in 4.5.15 regarding restrictions on the usage of analog operators.)

analog_conditional_statement ::=

// from A.6.6

if ( analog_expression ) analog_statement_or_null

 

{ else if ( analog_expression ) analog_statement_or_null }

 

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Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera

 

Version 2.3.1, June 1, 2009

VERILOG-AMS

[ else analog_statement_or_null ]

Syntax 5-8—Syntax of conditional statement

If the expression evaluates to True (that is, has a non-zero value), the analog statements specified as part of the true conditional shall be executed. If it evaluates to False (has a zero value (0)), the analog statements specified as part of the true conditional shall not be executed. If analog statements are specified as part of the false condition using else and expression is False, these statements shall be executed.

Since the numeric value of the if expression is tested for being zero (0), certain shortcuts are possible (see 4.2).

5.8.2 Examples

For example, the following two statements express the same logic:

if (expression)

if (expression != 0)

Because the else part of an if-else is optional, there can be confusion when an else is omitted from a nested if() sequence. This is resolved by always associating the else with the closest previous if() which lacks an else.

In the example below, the else goes with the inner if(), as shown by indentation.

if (index > 0) if (i > j)

result = i;

else // else applies to preceding if result = j;

If that association is not desired, a begin-end shall be used to force the proper association, as shown below.

if (index > 0) begin if (i > j)

result = i;

end

else result = j;

Nesting of if statements (known as an if-else-if construct) is the most general way of writing a multi-way decision. The expressions are evaluated in order; if any expression is True, the statement associated with it shall be executed and this action shall terminate the whole chain. Each statement is either a single statement or a sequential block of statements.

5.8.3 Case statement

The case statement is a multi-way decision statement which tests if an expression matches one of a number of other expressions, and if so, branches accordingly. The case statement has the syntax shown in Syntax 5-9.

analog_case_statement ::=

// from A.6.7

case ( analog_expression ) analog_case_item { analog_case_item } endcase

 

| casex ( analog_expression ) analog_case_item { analog_case_item } endcase

 

| casez ( analog_expression ) analog_case_item { analog_case_item } endcase

 

Copyright © 2009 Accellera Organization, Inc.

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