9.3 System tasks/functions executing in the context of the Analog Simulation Cycle

From 8.2, the analog simulation cycle has some different characteristics than the digital simulation cycle in VerilogAMS HDL. These differences requires some additional description for certain system tasks or functions that are supported in IEEE std 1364-2005 Verilog HDL and have been extended to work in the analog context by VerilogAMS HDL.

A key difference is that the analog engine iteratively evaluates the analog blocks in an analog macro process until that process is converged 8.3. The behavior of a particular system task or function during the iterative evaluation process will be stated in the relevant section for that system task or function, if required. The goal of the defined behavior of a system task or function in the analog context is that a call to a such system task or function in an analog block during an iteration that is rejected should cause no side-effects on the next iteration.

Another difference is that the analog engine supports additional analyses beyond a single transient analysis. A single transient analysis is the only analysis that IEEE std 1364-2005 Verilog HDL supports. Verilog AMS HDL extends this to allows multiple analyses, including multiple transient analyses, to be run within a single simulation process. Because of this extension, the behavior of a particular system task or function during different analysis types and between different analyses will be stated in the relevant section for that system task or function, if required.

9.4 Display system tasks

9.4.1 Behavior of the display tasks in the analog context

Verilog-AMS HDL extends the display tasks so that they can be used in the analog context.

The syntax for these functions are shown in Syntax 9-1.

display_tasks_in_analog_block ::= $strobe ( list_of_arguments ) ;

| $display ( list_of_arguments ) ; | $monitor ( list_of_arguments ) ; | $write ( list_of_arguments ) ;

| $debug ( list_of_arguments ) ;

Syntax 9-1—Syntax for the display_tasks_in_analog_block

The following rules apply to these functions.

—$strobe provides the ability to display simulation data when the simulator has converged on a solution for all nodes.

—$strobe displays its arguments in the same order they appear in the argument list. Each argument can be a quoted string, an expression which returns a value, or a null argument.

—The contents of string arguments are output literally, except when certain escape sequences are inserted to display special characters or specify the display format for a subsequent expression.

—Escape sequences are inserted into a string in three ways:

—The special character \ indicates the character to follow is a literal or non-printable character (see Table 9-20).

—The special character % indicates the next character shall be interpreted as a format specification which establishes the display format for a subsequent expression argument (see Table 9-21).

For each % character which appears in a string, a corresponding expression argument shall be supplied after the string.

—The special character string %% indicates the display of the percent sign character (%) (see Table 9-20).

—Any null argument produces a single space character in the display. (A null argument is characterized by two adjacent commas (,,) in the argument list.)

—When $strobe is invoked without arguments, it simply prints a newline character.

The $display task provides the same capabilities as $strobe. The $write task provides the same capabilities as $strobe, but with no newline. The $monitor task provides the same capabilities as $strobe, but outputs only when an argument changes. The $debug task provides the capability to display simulation data while the analog simulator is solving the equations; it displays its arguments for each iteration of the analog solver.

9.4.2 Escape sequences for special characters

The escape sequences shown in Table 9-20, when included in a string argument, print special characters.

Table 9-20— Escape sequences for printing special characters

9.4.3 Format specifications

Table 9-21 shows the escape sequences used for format specifications. The special character % indicates that the next character should be interpreted as a format specification that establishes the display format for a subsequent expression argument. For each % character (except %m, %% and %l) that appears in a string, a corresponding expression argument shall be supplied after the string.

Table 9-21— Escape sequences for format specifications

The formatting specification %l (or %L) is defined for displaying the library information of the specific module. This information shall be displayed as “library.cell" corresponding to the library name from which the current module instance was extracted and the cell name of the current module instance. See Clause 13 of IEEE std 1364-2005 Verilog HDL for information on libraries and configuring designs.

Any expression argument which has no corresponding format specification is displayed using the default decimal format in $strobe.

The format specifications in Table 9-22 are used for real numbers and have the full formatting capabilities available in the C language. For example, the format specification %10.3g sets a minimum field width of 10 with three (3) fractional digits.

Table 9-22— Format specifications for real numbers

9.4.4 Hierarchical name format

The %m format specifier does not accept an argument. Instead, it causes the display task to print the hierarchical name of the module, task, function, or named block which invokes the system task containing the format specifier. This is useful when there are many instances of the module which call the system task. One obvious application is timing check messages in a flip-flop or latch module; the %m format specifier pinpoints the module instance responsible for generating the timing check message.

9.4.5 String format

The %s format specifier is used to print ASCII codes as characters. For each %s specification which appears in a string, a corresponding argument shall follow the string in the argument list. The associated argument is interpreted as a sequence of 8-bit hexadecimal ASCII codes, with each 8 bits representing a single character. If the argument is a variable, its value shall be right-justified so the right-most bit of the value is the leastsignificant bit of the last character in the string. No termination character or value is required at the end of a string and leading zeros (0) are never printed.

9.4.6 Behavior of the display tasks in the analog block during iterative solving

All the display tasks, except $debug, shall not display output unless an iteration has been accepted.

9.4.7 Extensions to the display tasks in the digital context

For $strobe, $display, $write and $monitor

—the %r (or %R) format specifier may be used on real expressions in the digital context

9.5File input-output system tasks and functions

Verilog-AMS HDL extends many of the file operation tasks so that they can be used in the analog context. This section describes the File I/O tasks that can be used in the analog context.