- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example
Virtuoso AMS Environment User Guide
Variables for ams.env Files
amsDirect.simcntl |
useScwritefinal |
boolean |
t |
amsDirect.vlog |
allowDeviantBuses |
cyclic |
"no" |
amsDirect.vlog |
allowIllegalIdentifiers |
cyclic |
"warn" |
amsDirect.vlog |
allowNameCollisions |
cyclic |
"warn" |
amsDirect.vlog |
allowSparseBuses |
cyclic |
"warn" |
amsDirect.vlog |
amsEligibleViewTypes |
string |
"schematic" |
amsDirect.vlog |
checkAndNetlist |
boolean |
nil |
amsDirect.vlog |
checkOnly |
boolean |
nil |
amsDirect.vlog |
compileAsAMS |
boolean |
t |
amsDirect.vlog |
excludeViewNames |
string |
"" |
amsDirect.vlog |
headerText |
cyclic |
"none" |
amsDirect.vlog |
ifdefLanguageExtensions |
boolean |
nil |
amsDirect.vlog |
includeFiles |
string |
"(disciplines.vams)" |
amsDirect.vlog |
ncvlogArguments |
string |
"" |
amsDirect.vlog |
netlistAfterCdfChange |
boolean |
nil |
amsDirect.vlog |
paramDefVals |
string |
"" |
amsDirect.vlog |
paramGlobalDefVal |
string |
"0" |
amsDirect.vlog |
processViewNames |
string |
"" |
amsDirect.vlog |
prohibitCompile |
boolean |
nil |
amsDirect.vlog |
templateFile |
string |
"" |
amsDirect.vlog |
templateScript |
string |
"" |
amsDirect.vlog |
useDefparam |
boolean |
nil |
amsDirect.vlog |
useNowarn |
boolean |
t |
amsDirect.vlog |
useProcessViewNamesOnly |
boolean |
nil |
amsDirect.vlog |
verboseUpdate |
boolean |
t |
amsDirect.vlog |
checktasks |
boolean |
nil |
amsDirect.vlog |
ieee1364 |
boolean |
nil |
amsDirect.vlog |
noline |
boolean |
nil |
amsDirect.vlog |
incdir |
string |
"" |
amsDirect.vlog |
lexpragma |
boolean |
nil |
amsDirect.vlog |
logFileAction |
cyclic |
"Overwrite log file" |
amsDirect.vlog |
macro |
string |
"" |
amsDirect.vlog |
markcelldefines |
boolean |
nil |
amsDirect.vlog |
netlistUDFAsMacro |
boolean |
nil |
amsDirect.vlog |
bindCdsAliasLib |
boolean |
t |
amsDirect.vlog |
bindCdsAliasView |
boolean |
t |
amsDirect.vlog |
maxErrors |
int |
50 |
amsDirect.vlog |
messages |
boolean |
nil |
amsDirect.vlog |
neverwarn |
boolean |
nil |
amsDirect.vlog |
nomempack |
boolean |
nil |
amsDirect.vlog |
nopragmawarn |
boolean |
nil |
amsDirect.vlog |
nostdout |
boolean |
nil |
amsDirect.vlog |
nowarn |
string |
"" |
amsDirect.vlog |
pragma |
boolean |
nil |
amsDirect.vlog |
status |
boolean |
nil |
amsDirect.vlog |
update |
boolean |
t |
amsDirect.vlog |
vloglinedebug |
boolean |
nil |
amsDirect.vlog |
ncvlogUseAddArgs |
boolean |
nil |
amsDirect.vlog |
iterInstExpFormat |
string |
"%b_%i" |
amsDirect.vlog |
netClashFormat |
string |
"%b_netclash" |
amsDirect.vlog |
instClashFormat |
string |
"%b_instclash" |
amsDirect.vlog |
aliasInstFormat |
string |
"ams_alias_inst_%i" |
Detailed Descriptions of ams.env Variables
The next sections discuss each of the ams.env file variables in detail. The sections are arranged alphabetically by variable.
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Variables for ams.env Files
aliasInstFormat
Specifies the format to be used to create instances of thecds_alias module.
Syntax
amsDirect.vlog aliasInstFormat string "format"
Values |
|
|
format |
All characters, except those listed below, are printed exactly as |
|
|
included in format. The following characters have the |
|
|
indicated special meanings. |
|
|
%i |
Index number of the current cds_alias |
|
|
instance |
|
%% |
Prints the % character |
The default value of format is ams_alias_inst_%i, which produces names such as ams_alias_inst_1, ams_alias_inst_2, and so on.
If the resulting name is illegal in Verilog-AMS, the name is mapped. If the mapped name clashes with the name of another object, the name undergoes collision mapping.
Example
amsDirect.vlog aliasInstFormat string "cds_alias_%i"
Tells AMS netlister to create instance names with a suffixed index number. In this example, instances of the cds_alias module are given names like:
cds_alias_1 cds_alias_2 cds_alias_3
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Variables for ams.env Files
allowDeviantBuses
Controls the netlisting of bus specifications when there are conflicting bus ranges. Bus ranges conflict when, in references to the same bus, the indexes sometimes go from smaller to larger and other times go from larger to smaller.
Syntax
amsDirect.vlog allowDeviantBuses cyclic "no" | "warn" | "yes
Values |
|
no |
Netlisting halts immediately when the AMS netlister encounters |
|
conflicting bus ranges. This is the default. This value |
|
corresponds to the No – Print Errors value used in the |
|
graphical user interface (GUI). |
warn |
Netlisting continues when the AMS netlister encounters |
|
conflicting bus ranges if it is possible to create a valid netlist. The |
|
AMS netlister tells you how the non-compliant bus data is |
|
transformed. The generated netlist is likely to be less readable |
|
than one created from compliant bus data. This value |
|
corresponds to the Yes – Print Warnings value used in the |
|
GUI. |
yes |
Netlisting continues when the AMS netlister encounters |
|
conflicting bus ranges if it is possible to create a valid netlist. The |
|
AMS netlister does not issue a warning. This value corresponds |
|
to the Yes – Silently value used in the GUI. |
Example
An example of conflicting bus ranges in CDBA data is shown below:
a<0:7>
a<7:6>
a<5:0>
a<2:4>
The same example in Verilog-AMS is shown below:
a[0:7]
{a[7],a[6]}
{a[5],a[4],a[3],a[2],a[1],a[0]}
a{2:4}
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Variables for ams.env Files
Using the variable
amsDirect.vlog allowDeviantBuses cyclic "yes"
tells the AMS netlister to handle conflicting bus ranges whenever possible, without issuing a warning. This example sets the netlisting behavior for data netlisted into the Verilog® -AMS language.
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Variables for ams.env Files
allowIllegalIdentifiers
Controls the netlisting of non-compliant identifiers.
Syntax
amsDirect.vlog allowIllegalIdentifiers cyclic "no" | "warn" | "yes
Values |
|
no |
Netlisting halts immediately when the AMS netlister encounters |
|
a non-compliant identifier. This value corresponds to theNo – |
|
Print Errors value used in the graphical user interface (GUI). |
warn |
Maps non-compliant identifiers to names that are legal in the |
|
target language, and issues a warning telling you how the name |
|
is mapped. This is the default. This value corresponds to the |
|
Yes – Print Warnings value used in the GUI. |
yes |
Maps non-compliant identifiers to names that are legal in the |
|
target language. The AMS netlister does not issue a warning. |
|
This value corresponds to the Yes – Silently value used in the |
|
GUI. |
Description
If you specify warn or yes, the AMS netlister maps non-compliant identifiers to the target language. However, mapping identifiers results in a less readable netlist.
Identifiers are non-compliant if one or more of the following situations applies:
■Identifiers do not follow the syntax required by the netlist language you plan to use
■Identifiers are reserved words in the netlist language
For a list of Verilog-AMS reserved words, see the “Verilog-AMS Keywords” appendix, in the Cadence Verilog-AMS Language Reference.
■Identifiers do not map cleanly to the netlist language
■Identifiers are not unique within the design
Because the determination of non-compliance depends on the target netlist language, it is possible to have identifiers that are compliant for one target language and non-compliant for
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Variables for ams.env Files
another. To ensure that identifiers are compliant for every target netlist language, use the following syntax.
basic_identifier ::=
letter {[_] letter_or_digit}
letter_or_digit ::= a-z | 0-9
For example, the following identifiers are compliant for every target language.
an_identifier_name a_2nd_name a_name2
The following identifiers, because they do not use the suggested syntax, might be non-compliant for some target languages.
2identifier |
// Should |
begin with |
a letter. |
||||
My_identifer |
// Should |
not use |
uppercase |
letters. |
|||
an_identifier_ |
// |
Should |
end |
with a |
letter |
or digit. |
|
a&b |
// |
Should |
not |
use |
characters other than a-z, 0-9, and underscore. |
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