Virtuoso AMS Environment User Guide
Preparing a Design for Simulation
Editing an Analog Model File
To edit the contents of a model file listed in the table,
Highlight the row that lists the model file you want to edit, and clickEdit.
The model file opens in your selected editor.
Running AMS Design Prep
To run AMS Design Prep,
1.Choose AMS – Design Prep from the Cadence hierarchy editor. The AMS Design Prep window appears.
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Preparing a Design for Simulation
The settings in this window determine when netlisting and compilation occur as you work with the CDBA cellviews in your design hierarchy.
Setting |
Behavior |
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Netlist |
Enables netlisting |
Incremental |
Netlists CDBA cellviews in the hierarchy only if their HDL |
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data is not synchronized with their CDBA data |
All |
Netlists all CDBA cellviews in the hierarchy, regardless of |
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whether their HDL data is synchronized with their CDBA |
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data |
Compile |
Enables compilation |
When netlisting |
Specifies that thencvlog compiler is to create or update |
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the cellview’s compiled data only if the cellview is netlisted |
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when you click Run |
All |
Specifies that, for each cellview used in the design, the |
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ncvlog or ncvhdl compiler is to compile the cellview, |
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whether or not the cell is netlisted in this run. |
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2.Set the appropriate options.
3.Click Run.
In accordance with your selections, AMS Design Prep performs some or all of the following tasks:
Creates or updates netlist data
Creates or updates compiled data
Creates or updates the cds_globals module for global signals
Declares or updates design variables
Reports information, warnings, and errors in the log file and in the hierarchy editor message pane
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While AMS Design Prep is running, the AMS Run Info progress indicator appears.
You can stop the AMS Design Prep run by clicking Stop.
After AMS Design Prep finishes, the AMS Design Prep - Summary window appears, displaying the following information:
■Success or failure of the design preparation
■How many design units were netlisted
■How many errors were found in the design
■How many new global signals were found
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■How many new design variables were found
AMS Design Prep detects whether you have generated or edited the cds_globals module. If you try to run AMS Design Prep when the data in the cds_globals module has been edited outside the hierarchy editor or has an error, AMS Design Prep issues a warning and asks for confirmation, as shown below.
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Preparing a Design for Simulation
Messages and Log Files
When AMS Design Prep runs, it displays messages in the Cadence hierarchy editor window.
For example, the hierarchy editor messages might look like this.
Netlisting amslib top schematic
Compiling verilog.vams in cellview amslib top schematic.
ncvlog: v3.150.(a1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. Netlisting amslib comparator schematic.
Compiling verilog.vams in cellview amslib comparator schematic.
ncvlog: v3.150.(a1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. Creating cds_globals module in amslib cds_globals top_config.
Compiling verilog.vams in cellview amslib cds_globals top_config.
ncvlog: v3.150.(a1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. Design preparation has completed successfully.
You can watch the hierarchy editor messages to see current information about the AMS Design Prep run. If errors are reported that you want to fix, you can stop the AMS Design Prep run by clicking Stop in the AMS Run Info progress indicator.
AMS Design Prep does not create it’s own log file. However, tools running under the control of AMS Design Prep do create log files. The AMS netlister creates a log file called, by default, ams_direct.log, and the NC Verilog and NC VHDL compilers create the ncvlog.log and ncvhdl.log files. You can view these log files easily by choosingAMS – Netlister Log File or AMS – Simulator Log Files from the hierarchy editor menu.
For example, the contents of a netlister (ams_direct.log) file might look like this.
@(#)$CDS: amsdirect version 4.4.6 04/05/2000 17:39 (machine) $ Copyright (c) 1999 Cadence Design Systems. All Rights Reserved.
Run date: Thu Apr 13 14:09:52 2000 Run time options used:
-mpshost machine.Cadence.COM -mpssession sudeshna -pid 2443
Info: Processing ("amslib" "top" "schematic") ...
Info: Verilog-AMS netlist successfully written to /mnt3/sudeshna/eureka/alpha/AMS_lib/amsLib/top/schematic/verilog.vams.
Info: Found 0 errors and 0 warnings.
Info: Processing ("amslib" "comparator" "schematic") ...
Info: Verilog-AMS netlist successfully written to /mnt3/sudeshna/eureka/alpha/AMS_lib/amsLib/comparator/schematic/
verilog.vams.
Info: Found 0 errors and 0 warnings.
How AMS Design Prep Handles Global Signals and
Design Variables
The values of global signals and design variables must be available throughout a design, not just within a single module. AMS Design Prep enables this capability by collecting global signals and design variables into a module called cds_globals.
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