Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

When to Use AMS Design Prep

You need to run AMS Design Prep once to prepare the entire design before the first simulation. After the first simulation, you need to run AMS Design Prep when

■The design needs netlist consistency checks

■You add or change one or more cellviews in your design and netlists are not automatically created for those views when you check and save your design

■You add new global signals or design variables to your design

If you are uncertain whether you need to run AMS Design Prep, go ahead and run it. Although it might cost you additional time, it never hurts to run AMS Design Prep on your entire design.

Not running AMS Design Prep reduces iteration time if you are certain that you have not introduced any new design variables or global signals. If you have introduced new design variables or global signals or have neglected to run the AMS netlister for a schematic, the elaboration step fails. That indicates that you need to run AMS Design Prep on your design.

Specifying the Behavior of AMS Design Prep

AMS Design Prep is a flexible tool that allows you to process your design in various ways. You can change how the tool operates by changing options.

Setting Options for Global Design Data

You can access the option settings for the AMS netlister and for AMS Design Prep by choosing AMS – Options – Global Design Data in the hierarchy editor. (If you need

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

information about installing the AMS menu item in the hierarchy editor, see “Preparing to Use AMS Designer from the Hierarchy Editor” on page 62.)

This section describes only the Global Design Data category. For information about the Netlister and Compiler categories, see “Specifying the Behavior of the Netlister and Compilers” on page 74. For information about the Elaborator and Simulator categories, see “Specifying the Behavior of the Elaborator, Simulator, and Waveform Viewer” on page 232. For information about the Waveforms category, see “Setting Waveform Selection Options” on page 274.

AMS Design Prep automatically generates the cds_globals cell that contains the global signals and design variables. The cell name, cds_globals, is fixed, but you can specify a library name and view name in the Global Design Data Module pane of the window.

The fields in theDefault Global Signal Declarations pane contain lists of signals. AMS Design Prep uses the values in these fields to assign default wire types and to select grounds. For example, if the supply1 field containsvdd! dvdd!, then when AMS Design Prep finds a new global signal nameddvdd!, it declares supply1 as the wire type for dvdd!.

Each list of signals must consist of strings, such as gnd!, vdd!, or agnd!.

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

Note that a specification in the AMS Global Signals window overrides, for that signal, the default settings from the Default Global Signal Declarations pane. The AMS Global

Signals window is discussed in the next section.

Specifying Global Signals

Global signals can come from master CDBA (schematic) data or from out-of-module references in master Verilog (digital) or Verilog-AMS HDL data. AMS Design Prep is aware of only global signals that come from master CDBA data. You can use the AMS Global Signals window to declare a signal that is used as an out-of-module signal reference in the master

Verilog (digital) or Verilog-AMS HDL data.

AMS Designer implements global signals as out-of-module references, but does not support out-of-module references either into or out of VHDL-AMS design units. As a result, AMS Designer does not support using global signals in VHDL-AMS design units, even if you enter the VHDL-AMS global signals in the AMS Global Signals window.

When you make changes in the AMS Global Signals window and click OK, AMS Design Prep

■Creates and compiles the cds_globals module if it does not already exist.

■Regenerates and recompiles the cds_globals module if it does already exist.

To display the AMS Global Signals window, select AMS – Global Signals.

The display color of the entries in the Signal and Language fields indicates if AMS Design

Prep found the signal, or if you added it. If you added the signal, it is displayed in blue, and if it is found by AMS Design Prep, it is displayed in black.

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

The black color means that you cannot remove that signal; you cannot remove a global signal found by AMS Design Prep or add a signal with the same name as a global signal found by

AMS Design Prep. However, if you added a global signal in a previous design session, and it has the same name as a global signal found by AMS Design Prep during the current design session, then the global signal that you added in the previous session is used, and it is displayed in black, so you cannot remove the signal. This behavior is useful when you change the configuration data while switching back and forth between behavioral and schematic views.

If AMS Design Prep cannot find a global signal in the CDBA data in the current run, but found it in a previous run, the signal is displayed in red. You can remove a signal that is displayed in red because it is not needed for the current design configuration.

If the controls are disabled, AMS Design Prep might be unable to write to the cds_globals module where the information in the window is stored. For more information, see “How AMS Design Prep Handles Global Signals and Design Variables” on page 225.

Adding a Global Signal

To add a global signal

1.Click Add.

2.Click in the Signal field for the new line that appears, and type the name of the signal you want to add.

3.Specify the language in which the signal is declared (CDBA, Verilog, Spectre,

SpectreHDL, or SPICE) in the Language field.

4.Choose a wire type from the drop-down menu that appears when you click on the Wire Type field.

You can choose one of the following wire types: wire, tri, wor, wand, trior, trand, trireg, tri0, tri1, supply0, or supply1.

5.Enter the discipline in the Discipline field.

The discipline specification that you enter in this field is written to thecds_globals module. If you do not specify a discipline, no discipline specification is written to the cds_globals file and the discipline of the signal is determined by discipline resolution during elaboration.

For more information, see the “Disciplines” section, in the “Data Types and Objects” chapter, of the Cadence Verilog-AMS Language Reference.

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

6.If you want to use the global signal as a ground reference, select the ground option by clicking in the check box in the Ground field for the appropriate signal.

Deleting a Global Signal

To remove a global signal, select the signal by clicking on any field associated with the signal you want to remove, and then click Remove.

Aliasing and Unaliasing Global Signals

You can alias global signals into groups. Aliased signals in a group are electrically equivalent, as if they are joined by a wire. For more information, see “How Aliased Signals Are Netlisted” on page 131.

Aliasing Global Signals

To alias signals

1.Select the signals to be aliased, and click Alias.

To select signals listed consecutively, hold down the shift key while you click on the signal names to be aliased. To select signals that are not listed sequentially, hold down the control key while you click on the signal names. When you alias signals, they redisplay consecutively in the global signal list, joined by a vertical connecting bar, as shown in the example below.

If you alias signals belonging to separate aliased signal groups, all of the signals in the groups are aliased.