Virtuoso AMS Environment User Guide

Netlisting

(* integer library_binding = "amslib";

integer cds_net_set[0:1]= {"xground","vdd"};

integer xground[0:1] = {"new_ground","cds_globals.\\gnd5! "}; integer vdd = "cds_globals.\\3.3v! "; *)

‘endif

I2 ( .inn( dacOut ), .inp( holdSig ), .out( compOut ) );

INCA is a predefined compiler directive in thencvlog compiler, so you do not need to define it. See “Setting erilogV-AMS Options for the Netlister” on page 79 for more information.

Note: Even though omitting attributes allows compilation to succeed, the simulation results might be incorrect without the connection information found in the attributes.

How Aliased Signals Are Netlisted

Schematics often have nets of different names or different widths that carry the same signals. In a process called aliasing, the AMS netlister automatically uses instances of the cds_alias module to connect such nets while retaining their original names. (Retaining the original names facilitates cross-probing.) The netlister uses aliasing when connecting

■Differently named nets of a common width that all carry the same signal.

■A terminal of one width to a net of the same name but of a different width.

Modules that use aliased ports (as, for example, when the same name appears more than once in the list of port names) cannot instantiate other objects within themselves.

The cds_alias module that the netlister instantiates is implemented as follows:

// Verilog HDL for "basic", "cds_alias" "functional"

module cds_alias(a,a); parameter width = 1; inout [width-1:0] a;

endmodule

AMS Designer instantiates this module as necessary in the cds_globals module or in cellview netlists created by the netlister. For example, to alias signal2 and signal3, the netlister automatically places the following instantiation in the netlist.

cds_alias #(.width(1))

(* integer library_binding = "basic"; integer view_binding = "functional"; *)

ams_alias_inst_0 (signal2, signal3);

The library_binding and view_binding attributes are included by default to specify the binding for the cds_alias module. You can use ams.env variables to control whether the netlister writes these attributes. For more information, see “bindCdsAliasLib” on page 389 and “bindCdsAliasView” on page 390.

Virtuoso AMS Environment User Guide

Netlisting

How m-factors (Multiplicity Factors) Are Netlisted

An m-factor is a value that can be inherited down a hierarchy of instances. Circuit designers use m-factors to mimic parallel copies of identical devices without having to instantiate large sets of devices in parallel. The value of the inherited m-factor in a particular module instance is the product of the m-factor values in the ancestors of the instance and of the m-factor value in the instance itself. If there are no passed m-factors in the instance or in the ancestors of the instance, the value of the m-factor is one.

To identify m-factors, the AMS netlister notes the parameters required by each instance in the design and assumes that any such parameter with the name m is an m-factor. The m-factor parameter might be an instance property or a component parameter. To implement the m-factor capability, the netlister adds the passed_mfactor attribute to the corresponding instance statement in the netlist. For more information about the language attributes that AMS Designer provides to support m-factors, see the “Using an m-factor (Multiplicity Factor)” section of chapter 10, in the Cadence Verilog-AMS Language Reference.

For example, you have a symbol for the pmos4 model and the symbol has the following CDF parameters. In this form, Multiplier is the prompt for the CDF parameter named m, which is the m-factor for this model.

The netlister creates a netlist that includes the following instance statement.

pmos4 #(.m(2), .region("triode"), .w(20u), .l(3u)) (* integer library_binding = "amslib";

integer cds_net_set[0:0]= {"bulk_n"}; integer bulk_n = "cds_globals.\\vdd! "; integer passed_mfactor = "m"; *)

M11 ( net92, cds_globals.„nd! , net79, cds_globals.\vdd! );

Notice how the first line of the netlist fragment passes the value 2 for the parameterm. Also, notice in the fifth line, how thepassed_mfactor attribute identifies the parameterm as an m-factor. A similar attribute appears in each instance statement that instantiates the pmos4 model.

Virtuoso AMS Environment User Guide

Netlisting

How Iterated Instances Are Netlisted

An iterated instance is a single instance that represents multiple logical copies. An iterated instance has a name of the form I<3:1>, which specifies the number of logical copies to be created. Although the logical copies are not explicitly present in the design, they function as design elements with implicit connections to other elements of the design. When the amsScalarInstances variable is set to t, as it is by default, the AMS netlister expands each iterated instance into multiple instances.

For example, you have the following top-level schematic called iter_top, which includes an instance of the cell iter_master. The name of the instance, I<3:1>, indicates that this is an iterated instance representing three logical instances.

As the AMS netlister processes this design, it expands the iterated instance, generating the following netlist.

//Verilog-AMS netlist generated by the AMS netlister.

//Cadence Design Systems, Inc.

‘include "disciplines.vams" ‘include "constants.vams"

endmodule