Virtuoso AMS Environment User Guide
Elaborating, Simulating, and Plotting Results
Specifying the Behavior of the Elaborator, Simulator, and
Waveform Viewer
The elaborator, simulator, and waveform viewer support many different options, which allow you to tailor the behavior of the tools to your needs. All of the supported options can be set on the command line when you start the tools. In addition, you can set the most commonly used options by making selections in the graphical interfaces provided by the AMS environment. The following sections describe how to use the graphical interfaces to set options, elaborate designs, and simulate designs. For information about using the command line controls, see the Virtuoso AMS Simulator User Guide.
For more information, see the following sections.
■“Setting Elaborator Options” on page 232
■“Setting Simulator Options” on page 247
■“Setting Waveform Selection Options” on page 274
Setting Elaborator Options
You can access the option settings for the elaborator from the Cadence® hierarchy editor.
1.From the hierarchy editor, choose AMS – Options.
If the AMS menu entry is not visible, follow the instructions in “Preparing to Use AMS Designer from the Hierarchy Editor” on page 62.
The AMS Options window appears.
2.Expand the Elaborator category to find the options you want to change.
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The Elaborator category has the following subcategories.
3.Highlight the category that you want to change.
The corresponding pane appears. For information about the fields in each pane, see the following cross-references:
For information about this category |
See |
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Elaborator |
“Specifying General Options for the |
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Elaborator” on page 233 |
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Verilog |
“Specifying erilogV Options for the |
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Elaborator” on page 235 |
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VHDL |
“Specifying VHDL Optionsorf the |
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Elaborator” on page 237 |
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Timing |
“Specifying Timing Optionsorf the |
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Elaborator” on page 239 |
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SDF Annotation |
“SpecifyingSDF Annotation Options for |
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the Elaborator” on page 243 |
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Messages/Errors |
“SpecifyingMessage and Error Options |
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for the Elaborator” on page 246 |
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Specifying General Options for the Elaborator
1. Choose AMS – Options from the hierarchy editor menu.
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If the AMS menu entry is not visible, follow the instructions in “Preparing to Use AMS Designer from the Hierarchy Editor” on page 62.
2. Highlight Elaborator to open the AMS Options window to the Elaborator pane.
3.Fill in and select fields as necessary.
The following table briefly describes the fields. For more information, see the“ncelab Command Syntax and Options” section in the “Elaborating” chapter of theVirtuoso AMS Simulator User Guide.
Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
Maximum number of |
-errormax |
Specifies the maximum number of |
errors |
|
errors to process. |
Log file |
-append_log, |
Determines whether a log file is to |
|
-nolog |
be created, and, if so, whether the |
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|
new information is to overwrite any |
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existing log or be appended. |
Update design units |
-update |
Automatically recompiles any out- |
if needed |
|
of-date design units and then re- |
|
|
elaborates the design. |
Ignore source file |
-nosource |
Turns off source file timestamp |
timestamps when |
|
checking when the Update design |
using -update |
|
units if needed field is turned on. |
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Field |
Corresponding ncelab |
Effect |
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Option |
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Default discipline |
-discipline |
Specifies the discipline of discrete |
|
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nets for which a discipline is |
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otherwise undefined. |
Use detailed |
-dresolution |
Specifies the kind of discipline |
discipline resolution |
|
resolution to be used. |
Default timescale |
-timescale |
Sets the default timescale for |
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|
Verilog modules that do not have a |
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timescale set. |
Allow undefined |
-noparamerr |
Tells the elaborator to allow |
parameters |
|
undeclared parameters to be |
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overridden. |
Additional |
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To pass the elaborator any |
arguments |
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arguments that cannot be |
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generated by the AMS Options GUI, |
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|
you can type the options into this |
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field. |
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4. Click OK to save your changes.
Specifying Verilog Options for the Elaborator
To specify Verilog options for the elaborator,
1. From the Cadence hierarchy editor, choose AMS – Options.
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2.In the AMS Options window, choose Elaborator – Verilog to open the AMS Options window to the Verilog pane.
3.Select and fill in fields as necessary.
The following table briefly describes the fields. For more information, see the“ncelab Command Syntax and Options” section in the “Elaborating” chapter of theVirtuoso AMS Simulator User Guide.
Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
Access visibility |
-access |
Sets the visibility access for all |
|
|
objects in the design. |
Use an access file |
-afile |
Specifies an access file. |
Generate an access |
-genafile |
Generate an access file for PLI |
file |
|
and Tcl. |
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Field |
Corresponding ncelab |
Effect |
|
Option |
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OMI checking level |
-omicheckinglevel |
Specifies the OMI checking level |
|
|
to use. |
Run IEEE 1364 lint |
-ieee1364 |
Checks for compatibility with the |
checker |
|
IEEE 1364 standard. |
Expand all vector nets |
-expand |
Expands all vector nets. |
PLI Options |
|
|
Dynamically load |
-loadvpi |
Dynamically loads the specified |
VPI libraries |
|
VPI application. |
Dynamically load |
-loadpli1 |
Dynamically loads the specified |
PLI libraries |
|
PLI 1.0 application. |
Enable delay |
-anno_simtime |
Enables the use of PLI/VPI |
annotation at |
|
routines that modify delays at |
simulation time |
|
simulation time. |
Suppress VPI/PLI |
-plinowarn |
Disables printing of PLI warning |
warning and error |
|
and error messages. |
messages |
|
|
Suppress VPI/PLI |
-plinooptwarn |
Prints a warning message only |
messages caused |
|
the first time that a PLI read, |
by optimizations |
|
write, or connectivity access |
|
|
violation is detected. |
|
|
|
4. When you are done changing options, click OK to save your changes.
Specifying VHDL Options for the Elaborator
To specify VHDL options for the elaborator,
1. From the Cadence hierarchy editor, choose AMS – Options – Elaborator.
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2.In the AMS Options window, choose Elaborator – VHDL to open the AMS Options window to the VHDL pane.
3.Select and fill in fields as necessary.
The following table briefly describes the fields. For more information, see the“ncelab Command Syntax and Options” section in the “Elaborating” chapter of theVirtuoso AMS Simulator User Guide.
Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
Enable VHDL 93 |
-v93 |
Enables VHDL-93 features. |
features |
|
|
Use 5X configs for |
-use5x4vhdl |
Specifies that configurations apply |
VHDL |
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to VHDL as well as Verilog-AMS |
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and that configurations take |
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precedence over VHDL default |
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binding and other searches. |
Preserve resolution |
-preserve |
Preserves resolution functions on |
functions on signals |
|
signals with only one driver. |
with only one driver |
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|
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Field |
Corresponding ncelab |
Effect |
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Option |
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|
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Enable relaxed |
-relax |
Makes design units visible for |
interpretation of |
|
default binding when the design |
VHDL LRM |
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units exist in a library that has not |
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been made visible with a LIBRARY |
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declaration in the VHDL source and |
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when the design units do not exist |
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in the library that has been defined |
|
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as the work library. |
Allow mixed-case, |
-mixesc |
Enables elaboration of mixed- |
escaped identifiers |
|
language designs in which escaped |
in VHDL |
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names are used for VHDL or |
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VHDL-AMS entities imported into |
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Verilog or Verilog-AMS designs. If |
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you follow the AMS Designer |
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guideline that recommends using |
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lower case identifiers, this option is |
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unnecessary. For more information, |
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see “ncelabMixEsc” on page 439. |
Specify value for top |
-generic |
Specifies a value for a top-level |
level generic |
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generic. |
|
|
|
4. When you are done changing options, click OK to save your changes.
Specifying Timing Options for the Elaborator
To specify timing options for the elaborator,
1. From the Cadence hierarchy editor, choose AMS – Options.
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2.In the AMS Options window, choose Elaborator – Timing to open the AMS Options window to the Timing pane.
3.Select and fill in fields as necessary.
The following table briefly describes the fields. For more information, see the“ncelab Command Syntax and Options” section in the “Elaborating” chapter of theVirtuoso
AMS Simulator User Guide.
Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
Disable timing checks |
-notimingchecks |
Turns off the execution of timing |
|
|
checks. |
Suppress timing check |
-no_tchk_msg |
Turns off the display of timing |
warnings |
|
check warning messages. |
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Field |
Corresponding ncelab |
Effect |
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|
Option |
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Print convergence |
-ntc_warn |
Print convergence warnings for |
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warnings for negative |
|
negative timing checks for both |
|
time checks |
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Verilog and VITAL if delays |
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|
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cannot be calculated given the |
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current limit values. |
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Verilog Timing Options |
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Delay mode |
-delay_mode |
Specifies the delay mode to be |
|
|
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used for digital Verilog-AMS |
|
|
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portions of the hierarchy. |
|
Disable enhanced |
-disable_enht |
Turns off the enhanced timing |
|
timing features |
|
features enabled by using |
|
|
|
special properties in a specify |
|
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block. |
|
Disallow negative |
-noneg_tchk |
Disallows negative values in |
|
values in checks |
|
$setuphold and $recrem |
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timing checks in the Verilog |
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description and in SETUPHOLD |
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and RECREM timing checks in |
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SDF annotation. |
|
Enable |
-pathpulse |
Enables PATHPULSE$ |
|
PATHPULSE$ |
|
specparams, which are used to |
|
specparams |
|
set module path pulse control on |
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a specific module or on specific |
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paths within modules. |
|
Pulse reject limit |
-pulse_r |
Sets the percentage of delay for |
|
(path and |
|
the pulse reject limit for both |
|
interconnect) |
|
module paths and interconnect. |
|
Pulse reject limit |
-pulse_int_r |
Sets the percentage of delay for |
|
(interconnect |
|
the pulse reject limit for |
|
only) |
|
interconnect only. |
|
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Field |
Corresponding ncelab |
Effect |
|
Option |
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|
|
|
Relax tcheck data |
-extend_tcheck_ |
Extends the violation regions |
limit by |
data_limit |
established by a pair of |
|
|
$setuphold or $recrem |
|
|
timing checks with negative |
|
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values in which the timing |
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checks contain two different |
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constraints for posedge and |
|
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negedge of data with respect to |
|
|
the same reference signal and in |
|
|
which the violation regions do |
|
|
not overlap. |
Error pulse |
-epulse_ondetect, |
Uses On-Detect or On-Event |
filtering |
-epulse_onevent |
filtering of error pulses. |
Ignore notifiers in |
-nonotifier |
Tells the elaborator to ignore |
timing checks |
|
notifiers in timing checks. |
Filter canceled |
-epulse_neg |
Filters cancelled events |
events to e state |
|
(negative pulses) to the e state. |
Pulse error limit |
-pulse_e |
Sets the percentage of delay for |
(path and |
|
the pulse error limit for both |
interconnect) |
|
module paths and interconnect. |
Pulse error limit |
-pulse_int_e |
Sets the percentage of delay for |
(interconnect |
|
the pulse error limit for |
only) |
|
interconnect only. |
Relax tcheck |
-extend_tcheck_ |
Extends the violation regions |
reference limit by |
reference_limit |
established by a pair of |
|
|
$setuphold or $recrem |
|
|
timing checks with negative |
|
|
values in which the timing |
|
|
checks contain two different |
|
|
constraints for posedge and |
|
|
negedge of data with respect to |
|
|
the same reference signal and in |
|
|
which the violation regions do |
|
|
not overlap. |
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Field |
Corresponding ncelab |
Effect |
|
Option |
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|
|
|
VHDL Timing Options |
|
|
Disable VITAL |
-novitalaccl |
Suppresses the acceleration of |
acceleration |
|
VITAL level 1 compliant cells. |
Disable X |
-no_tchk_xgen |
Turns off X generation in |
generation in |
|
accelerated VITAL timing |
VITAL timing |
|
checks. |
checks |
|
|
Disable X |
-no_vpd_xgen |
Turns off X generation in |
generation in |
|
accelerated VITAL pathdelay |
VITAL path |
|
procedures. |
delays |
|
|
Suppress VITAL |
-no_vpd_msg |
Turns off warning messages |
path delay |
|
from accelerated VITAL path |
warnings |
|
delay procedures. |
Ignore |
-noipd |
Turns off recognition of input |
interconnect |
|
path delays in a VITAL level 1 |
delays |
|
cell and uses the non-delayed |
|
|
input signals directly. |
|
|
|
4. When you are done changing options, click OK to save your changes.
Specifying SDF Annotation Options for the Elaborator
To specify SDF Annotation options for the elaborator,
1. From the Cadence hierarchy editor, choose AMS – Options.
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2.In the AMS Options window, choose Elaborator – SDF Annotation to open the AMS
Options window to the SDF Annotation pane.
3.Select and fill in fields as necessary.
The following table briefly describes the fields. For more information, see the“ncelab Command Syntax and Options” section in the “Elaborating” chapter of theVirtuoso AMS Simulator User Guide.
Field |
Corresponding ncelab |
Effect |
|
|
Option |
|
|
|
|
|
|
Use SDF command |
-sdf_cmd_file |
Specifies an SDF command file to |
|
file |
|
control SDF annotation. |
|
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Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
Delay type |
-mindelays, |
Applies the minimum, typical, or |
|
-typdelays, |
maximum delay value from a |
|
-maxdelays |
timing triplet in the form |
|
|
min:typ:max in the SDF file while |
|
|
annotating to Verilog or to VITAL. |
Suppress SDF |
-sdf_no_warnings |
Suppresses warning messages |
warnings |
|
from the SDF annotator. |
Allow unique delays |
-intermod_path |
Enables multisource and |
for each source-delay |
|
transport delay behavior with |
path |
|
pulse control for interconnect |
|
|
delays. |
Include detailed |
-sdf_verbose |
Includes detailed information in |
information in SDF log |
|
the SDF log file. |
file |
|
|
Round precision of |
-sdf_precision |
SDF data is modified to this |
timing in SDF file |
|
precision. |
Verilog SDF Options |
|
|
Suppress SDF |
-no sdfa_header |
Turns off the printing of elaborator |
command file |
|
information messages that |
information |
|
display information contained in |
messages |
|
the SDF command file. |
Disable celltype |
-sdf_nocheck_ |
Disables celltype validation |
validation |
celltype |
between the SDF annotator and |
between SDF |
|
the Verilog description. |
annotator and |
|
|
Verilog |
|
|
description |
|
|
Allow SDF worst- |
-sdf_worstcase_ |
For timing values in the SDF file, |
case rounding |
rounding |
truncates the min value, rounds |
|
|
the typ value, and rounds up the |
|
|
max value. |
Do not run |
-noautosdf |
Turns off automatic SDF |
$sdf_annotate |
|
annotation. |
tasks |
|
|
automatically |
|
|
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Field |
Corresponding ncelab |
Effect |
|
Option |
|
|
|
|
VHDL Timing Options |
|
|
Select delay |
-vipdmin, |
Selects the typical, minimum, or |
value for |
-vipdmax |
maximum delay value for |
VitalInterconnect |
|
VitalInterconnectDelays. |
Delays |
|
|
|
|
|
4. When you are done changing options, click OK to save your changes.
Specifying Message and Error Options for the Elaborator
To specify message and error options for the elaborator,
1.From the Cadence hierarchy editor, choose AMS – Options.
2.In the AMS Options window, choose Elaborator – Messages/Errors to open the AMS Options window to the Elaborator Messages/Errors pane.
3. Select and fill in fields as necessary.
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