
- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example

Virtuoso AMS Environment User Guide
Working with Schematic Designs
electrical (* integer supplySensitivity = "cds_globals.\\vdd! " ; *) \vdd! ; electrical (* integer groundSensitivity = "cds_globals.\\vss! " ; *) \vss! ;
reg temp; |
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always begin |
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// Do this always. |
|
if(V(aVal) > |
((V(\vdd! ) - V(\vss! ))/2 + 0.5 )) |
||
#1 |
temp |
= 1; |
// Delay 1 time unit,drive output 1. |
else if |
(V(aVal) < ((V(\vdd! ) - V(\vss! ))/2 -0.5)) |
||
#1 |
temp |
= 0; |
// or drive output 0, depending on aVal. |
else |
|
|
|
#1 |
temp |
= 1’bx; |
|
end |
|
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|
assign dVal = temp; |
// Bind register to digital output. |
endmodule
The next step is to specify the digital ports to which the connect module is sensitive. To do that, you add the groundSensitivity and supplySensitivity properties to the connected digital port. In the buffer string example illustrated above, connect modules are connected to both the input and the output ports of buffer bd2 and must therefore be sensitive to the supplies in those ports. In this case, the groundSensitivity and supplySensitivity properties must be added to both ports of the buffer, like this.
module bux2_5V (Z,A);
input
(* integer supplySensitivity="\\vdd! "; integer groundSensitivity="\\vss! "; *)
A ; output
(* integer supplySensitivity="\\vdd! "; integer groundSensitivity="\\vss! "; *)
Z;
wire \vss! ; wire \vdd! ;
analog begin
V(\vss! ) <+ 0.0 ; V(\vdd! ) <+ 5.0 ;
end
buf #1 (Z,A);
specify specparam
t_A_Z_rise = 0.1, t_A_Z_fall = 0.1;
// Delays
(A +=> Z) = (t_A_Z_rise,t_A_Z_fall); endspecify
endmodule
Making Connect Modules Sensitive to Inherited Connection Values
This section describes how to use the groundSensitivity and supplySensitivity properties to make a connect module sensitive to supplies whose values are set by inherited
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Virtuoso AMS Environment User Guide
Working with Schematic Designs
connections. You might use this capability, for example, when you want to be able to switch between two different power supplies and have connect modules act differently depending on a value that is provided by inherited connection.
The primary change involved in making the connect module sensitive to values that are determined by inherited connections, is to the declarations of the ports in the ordinary module to which the connect module is sensitive. You use inherited connections to set the values of the signals in the ports and use the sensitivity properties to make the connect module sensitive to those values.
The following example illustrates how to set up the inherited connections and sensitivities in the ordinary module. Sensitivities are specified for both the input and output ports,A, and Z, so that connect modules can be inserted across and be sensitive to the supplies in either or both of those ports.
module bux2 (Z,A);
input
(* integer supplySensitivity="\\vdd! "; integer groundSensitivity="\\vss! "; *)
A ; output
(* integer supplySensitivity="\\vdd! "; integer groundSensitivity="\\vss! "; *)
Z;
wire
(* integer inh_conn_prop_name="lSup";
integer inh_conn_def_value="cds_globals.\\vss! "; *)
\vss! ; wire
(* integer inh_conn_prop_name="hSup";
integer inh_conn_def_value="cds_globals.\\vdd! "; *)
\vdd! ;
buf #1 (Z,A);
‘ifdef functional ‘else
specify specparam
t_A_Z_rise = 0.1, t_A_Z_fall = 0.1;
// Delays
(A +=> Z) = (t_A_Z_rise,t_A_Z_fall); endspecify
‘endif
endmodule
Notice how the input port A has a specifiedsupplySensitivity signal name of "\\vdd! ". When a supplySensitive connect module is connected to this input port, the connect module becomes sensitive to the value of "\\vdd! ".
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Working with Schematic Designs
Next, consider how the value of "\\vdd! " is set. That value is set according to the inherited connections properties farther down in the module. For "\\vdd! " the relevant specification looks like this.
wire
(* integer inh_conn_prop_name="hSup";
integer inh_conn_def_value="cds_globals.\\vdd! "; *)
\vdd! ;
This statement establishes an inherited connection with the name hSup and the default value of "cds_globals.\\vdd! ". If the value of hSup is not set anywhere above this module, then the value of \vdd! is set to the value of "cds_globals.\\vdd! ". If inherited connections are used to set a different value for hSup, then \vdd! takes on the different value, which, because supplySensitivity is being used, can be passed on to a connected connect module.
The connect module is set up in the usual way to be sensitive to the value of "cds_globals.\\vdd! ". For example, you might prepare the following A2D module to connect to the digital input port A mentioned above.
‘include "disciplines.vams"
connectmodule elect2logic(aVal, dVal); output dVal;
input aVal; logic dVal; electrical aVal;
electrical (* integer supplySensitivity = "cds_globals.\\vdd! " ; *) \vdd! ; electrical (* integer groundSensitivity = "cds_globals.\\vss! " ; *) \vss! ;
reg temp; |
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|
|
always begin |
|
// Do this always. |
|
if(V(aVal) > |
((V(\vdd! ) - V(\vss! ))/2 + 0.5 )) |
||
#1 |
temp |
= 1; |
// Delay 1 time unit,drive output 1 |
else if |
(V(aVal) < ((V(\vdd! ) - V(\vss! ))/2 -0.5)) |
||
#1 |
temp |
= 0; |
// or drive output 0, depending on aVal. |
else |
|
|
|
#1 |
temp |
= 1’bx; |
|
end |
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assign dVal = temp; |
// Bind register to digital output. |
endmodule
With this preparation, you can then change the value of hSup and that changed value is inherited through the design. The sensitivity properties then make the attached connect modules sensitive to that changed value.
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