
- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example

Virtuoso AMS Environment User Guide
Working with Schematic Designs
netSet and is a legal net name, its value is used as the connecting net rather than the default net name specified in the expression.
Start at cellview containing net expression
Go up one level
No
Is there a cellview above?
Yes
Is there a netSet property on
the instance of this path?
No |
Use default net name |
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specified in the net |
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expression |
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Yes
Use value of the netSet property
The netSet property can be placed on any instance and it affects all net expression labels with matching property names at all levels below that instance unless overridden by another netSet property on a lower-level instance.
Net and Pin Properties
The AMS environment supports the following properties. The last three are in addition to those listed in “Properties” on page 610.
netType |
Specifies the type of a net. The type must be one of:supply0, |
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supply1, tri, tri0, tri1, triand, trior, trireg, wand, |
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wire, wor, wreal. For example, using the property |
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netType=wand on net a, results in net a being declared in the |
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netlist as |
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wand a; |
netDiscipline |
Specifies the discipline used to declare a net. This is sometimes |
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called net coercion. For example, using the property |
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netDiscipline=electrical on net a, results in net a being |
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declared in the netlist as |
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electrical a; |
groundSensitivity |
For information, see “groundSensitivity and supplySensitivity |
|
Properties” on page 173 |
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Working with Schematic Designs
supplySensitivity For information, see “groundSensitivity and supplySensitivity Properties” on page 173
groundSensitivity and supplySensitivity Properties
The groundSensitivity and supplySensitivity properties provide a way to make a connect module sensitive to supplies in the module to which the connect module is connected.
Typically the port of the connected module is a digital port. It is possible to make a connect module sensitive to supplies in an analog port but making the connect module sensitive to supplies in the connected digital port is much more likely to produce the behavior that you expect. This is so because:
■When the connect module converts analog signals to digital values, the decision to output a one or a zero depends on the relationship between the analog signal and a threshold value. The threshold value is determined by the supply values in the component that includes the connected digital port.
■When the connect module converts digital values to analog signals, the connect module needs to determine what voltage to produce for each digital input value. Again, that voltage depends on the supplies in the component that includes the connected digital port
Overview of the Sensitivity Properties
The groundSensitivity and supplySensitivity properties, which are added to a port or pin definition, have the following syntax.
sensitivity_properties ::=
(* [ integer groundSensitivity = "sig1_sensitive_to" ; ]
[ integer supplySensitivity = "sig2_sensitive_to" ; ] *)
sig1_sensitive_to, sig2sensitive_to
Names of signals, typically global signals, to which a connect module is made sensitive.
When the groundSensitivity property is included as part of a signal declaration in the connect module, the declared signal takes on, by default, the value of sig1_sensitive_to. When the groundSensitivity property is included as part of a signal declaration in an ordinary module, the sig1_sensitive_to value in that module overrides the sig1_sensitive_to value specified in the connect module. The supplySensitivity property works similarly.
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Working with Schematic Designs
For example, the connect module might be defined as follows.
connectmodule l_to_e(dval, aval);
...
electrical (* integer groundSensitivity = "global_pwr.pow1" ; *) gnd ;
...
endmodule
This connect module is connected to the digital port d in an ordinary module that is defined as follows.
module sample(d);
output (* integer groundSensitivity = "global_pwr.pow5" ; *) d ;
...
endmodule
In this example, gnd is defined in the connect module as taking on, by default, the value of global_pwr.pow1, but that value is overridden by the value global_pwr.pow5 specified in the module sample when the connect module is inserted across the digital port d. To generalize, if the groundSensitivity property is not used in the ordinary module, the connect module uses the default value specified on thegroundSensitivity property in the connect module.
Basic Principles for Using the Sensitivity Properties
Some basic principles will help you use the groundSensitivity and supplySensitivity properties correctly.
■Connect modules are always inserted between a digital port and an analog net. When you use the groundSensitivity and supplySensitivity properties, you make the connect module sensitive to the signals on the digital port. That is true whatever the direction of the port might be.
■There are two steps involved in establishing ground or supply sensitivity: inserting the necessary properties in the connect module; and adding the corresponding properties to the connected digital port. If the connected digital port is part of a schematic, you define the properties on the connected pin in the schematic. If the connected digital port is defined in a text module, you add the properties to the port definition in the module.
■The default value associated with the groundSensitivity and supplySensitivity properties must be the name of a signal, not the name of a property.
■You must use detailed discipline resolution or the sensitivity properties have no effect.
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Working with Schematic Designs
Example: Using the Sensitivity Properties in a Chain of Buffers
Assume that you have the following schematic containing three buffers. Buffers ba1 and ba3 are instances of a module that is implemented as an analog block with analog input and output pins. Buffer bd2 is implemented as a digital block, with logic input and output pins.
ba1 |
bd2 |
ba3 |
n1 |
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n2 |
elect2logic |
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logic2elect |
connect module |
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connect module |
During elaboration, connect modules are inserted across net n1 and the digital input port of buffer bd2, and across the digital output port of buffer bd2 and net n2.
Assume that the string of buffers is designed to run at 5.0 volts. The connect module must then be written to work at that voltage. For example, an A2D connect module with hardcoded thresholds set for 5.0 volts might look like this.
‘include "disciplines.vams" connectmodule elect2logic(aVal, dVal);
output dVal; input aVal; logic dVal; electrical aVal;
reg temp; |
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always begin |
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// Digital, do this always. |
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if(V(aVal) > |
3.0) |
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#1 |
temp |
= 1; |
// Delay 1 time unit,drive output 1 |
else if |
(V(aVal) < 2.0) |
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#1 |
temp |
= 0; |
// or drive output 0, depending on aVal. |
else |
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#1 |
temp |
= 1’bx; |
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end |
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assign dVal = temp; |
// Bind register to digital output. |
endmodule
But assume now that the string of buffers can run at either 3.0 volts or 5.0 volts, depending on the supplies that are provided. To make the connect module sensitive to the supplies, you use the groundSensitivity and supplySensitivity properties, and rewrite the always statement so that the threshold is calculated from the supply and ground values.
‘include "disciplines.vams"
connectmodule elect2logic(aVal, dVal); output dVal;
input aVal; logic dVal; electrical aVal;
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