Virtuoso AMS Environment User Guide

Preface

The Virtuoso® AMS environment part of Virtuoso AMS Designer provides a comfortable framework for developing, elaborating, simulating, and debugging blocks. This user guide discusses that environment and details how to make the best use of it.

The preface discusses the following:

■Related Documents on page 18

■Typographic and Syntax Conventions on page 19

Virtuoso AMS Environment User Guide

Preface

Related Documents

For more information about the AMS simulator and related products, consult the sources listed below.

■Cadence Analog Circuit Design Environment User Guide

■Cadence Mixed-Signal Circuit Design Environment

■NC Verilog Simulator Help

■NC VHDL Simulator Help

■SimVision Analysis Environment User Guide

■Virtuoso Spectre Circuit Simulator Reference

■Virtuoso Spectre Circuit Simulator User Guide

■Cadence Verilog-A Language Reference

■Cadence AMS Simulator User Guide

■Cadence Application Infrastructure User Guide

■Cadence Hierarchy Editor User Guide

■Cadence Library Manager User Guide

■Cadence Verilog-AMS Language Reference

■Component Description Format User Guide

■IEEE Standard VHDL Language Reference Manual (Integrated with VHDL-AMS Changes), IEEE Std 1076.1. Available from IEEE.

■Instance-Based View Switching Application Note

■Simvision Waveform Viewer User Guide

■Verilog-AMS Language Reference Manual. Available from Open Verilog International.

■Verilog-XL Reference

■Cadence VHDL-AMS Overview

■Virtuoso Schematic Editor User Guide

For information about problems, see the Virtuoso AMS Environment Known Problems and Solutions.

Virtuoso AMS Environment User Guide

Preface

Typographic and Syntax Conventions

Special typographical conventions are used to distinguish certain kinds of text in this document. The formal syntax used in this reference uses the definition operator,::= , to define the more complex elements of the Verilog-AMS language in terms of less complex elements.

■Lowercase words represent syntactic categories. For example,

module_declaration

Some names begin with a part that indicates how the name is used. For example,

node_identifier

represents an identifier that is used to declare or reference a node.

■Boldface words represent elements of the syntax that must be used exactly as presented (except as noted below). Such items include keywords, operators, and punctuation marks. For example,

endmodule

Sometimes options can be abbreviated. The shortest permitted abbreviation is shown by capital letters but you can use either upper or lower-case letters in your code. For example, the syntax

-CHecktasks

means that you can type the option as -checktasks, -CHECKTASKS, -ch, -CH, -cH, and so on.

■Vertical bars indicate alternatives. You can choose to use any one of the items separated by the bars. For example,

■Square brackets enclose optional items. For example,

input declaration ::=

input [ range ] list_of_port_identifiers ;

■Braces enclose an item that can be repeated zero or more times. For example,

list_of_ports ::=

( port { , port } )

■Code examples are displayed in constant-width font.

Virtuoso AMS Environment User Guide

Preface

/* This is an example of the font used for code.*/

■Within the text, variables are in italic font, like this: allowed_errors.

■Keywords, filenames, names of natures, and names of disciplines are set in constantwidth font, like this: keyword, file_name, name_of_nature, name_of_discipline.

■If a statement is too long to fit on one line, the remainder of the statement is indented on the next line, like this:

qgf = width*length*cfbb*(vgfs - wkf - qb/(2*cbb) - (vgbs - vfbb + qb/(2*cob))) + qgf_par ;

Virtuoso AMS Environment User Guide

1

Overview of the Virtuoso AMS Designer

Flow

The AMS Designer flow uses the AMS environment and a set of tools tuned to facilitate the development of mixed-signal designs. The flow gives you a mixed-signal, mixed-language, block-based design solution featuring the following characteristics.

■A top-down or bottom-up development methodology for both analog and mixed-signal designs.

■The ability to mix blocks at different levels of abstraction for an optimized balance of simulation accuracy versus speed

■The ability to create Verilog® -AMS netlists for an entire library with a single command

■Automatic, non-destructive conversion of existing analog primitive libraries

■A design capture environment that facilitates both text and schematic data entry

■Support for the Verilog-AMS, VHDL-AMS, Spectre® , and SPICE languages

■Flexible and accurate representation of analog/digital interface boundaries and accurate, automatic insertion of interface elements

■Flexible and accurate representation of mixed-language boundaries

■Flexible design configuration, which allows easy switching from one design representation to another

■Accelerated, automatic netlist generation from schematics

■A single debugging environment for analog, digital, and mixed-signal parts of your design

■Stand-alone simulation when desired

■A single unified waveform display for analog, digital, and mixed signal nets in your design

The tools in the AMS Designer flow work smoothly together, so you can move from one tool to another without worrying about whether your data is in the necessary format. For example,

when you work within the flow, you can develop a schematic, define a configuration, and then

Virtuoso AMS Environment User Guide

Overview of the Virtuoso AMS Designer Flow

simulate without working through a netlisting step: the flow netlists the design for you as needed or uses a netlist created by someone else for a block you are referencing.

There are many tools included in the AMS Designer flow. They are listed here, along with cross-references to detailed discussions of their capabilities.

The AMS Designer Flow Supports Both Analog and

Digital Designers

The AMS Designer flow presents a familiar face to both analog and digital designers. Analog designers often work in a graphical environment while digital designers tend to work in a textbased environment, relying on synthesis to transform their hardware description language

(HDL) descriptions into actual circuitry. The AMS Designer flow brings these two approaches together, so a designer who prefers to work with text always has up-to-date HDL representations of schematic designs.

This dual text and graphical approach is available throughout the flow for both analog and digital designs. For example, to follow an all text approach you might use a text editor to code an HDL module and use the ncvlog, ncelab, and ncsim commands to prepare and simulate the design. To follow a graphical approach, you might use the Virtuoso® schematic