Virtuoso AMS Environment User Guide

Netlisting

The AMS netlister translates this top-level schematic into the following Verilog-AMS netlist. In the netlist, notice the attributes (set off between (* and *)) used to pass information to the elaborator. Notice too, the out-of-module references to objects in the cds_globals module.

//Verilog-AMS netlist generated by the AMS netlister

//Cadence Design Systems, Inc.

‘include "disciplines.vams" ‘include "constants.vams"

module top ( );

vsource #(.type("dc"), .dc(3)) (*

integer library_binding = "analogLib"; *) V0 ( cds_globals.\vdd! , cds_globals.\gnd! );

vsource #(.type("dc"), .dc(-3)) (*

integer library_binding = "analogLib"; *) V1 ( cds_globals.\vss! , cds_globals.\gnd! );

vhdl_clock (* integer library_binding = "diglib"; *) I5 ( .out1( clkSig ) );

sareg (* integer library_binding = "diglib"; *) I3 ( .b2( b2 ),

.endOfConv( endOfConv ), .b5( b5 ), .b6( b6 ), .b3( b3 ), .b7( b7 ),

.b0( b0 ), .clkSig( clkSig ), .b4( b4 ), .b1( b1 ),

.result( compOut ), .trigger( endOfConv ) );

daconv #(.refVolt(5.000000)) (* integer library_binding = "amslib"; *) I4 ( .b2( b2 ), .b5( b5 ), .b6( b6 ), .b3( b3 ),

.compSig( dacOut ), .b7( b7 ), .b0( b0 ), .b4( b4 ), .b1( b1 ) );

signalSrc (* integer library_binding = "amslib"; *) I0 ( .sig( inSig ) );

comparator (* integer library_binding = "amslib"; *) I2 ( .inn( dacOut ),

.inp( holdSig ), .out( compOut ) );

samplehold (* integer library_binding = "amslib"; *) I1 ( .inSig( inSig ),

.holdSig( holdSig ), .trigger( endOfConv ) );

endmodule

The previous netlist does not illustrate how the AMS netlister handles inherited connections, which, as described in the following sections, are also translated as attributes.

How Inherited Connections Are Netlisted

An inherited connection is a net expression associated with either a signal or terminal. You use inherited connections to selectively override global names within your design.

The syntax for the net expression used in the Virtuoso® Schematic Editor is:

[@property_name:%:default_net_name]*

where property_name is the name of the property whose value can redefine the global signal name and default_net_name is the global signal name if it is not redefined by the specified property.Thedefault_net_name must not be a nested netlist property expression; if it is, the net expression is not evaluated.

Virtuoso AMS Environment User Guide

Netlisting

As described in the next sections, the AMS netlister translates the inherited connections information into attributes in the Verilog-AMS netlist. The AMS elaborator uses these attributes to resolve inherited connections in the same way that other DFII tools do.

See the “Inherited Connections” section, in the “Understanding Connectivity and Naming

Conventions” chapter of the Virtuoso Schematic Editor User Guide for detailed information about inherited connections.

Inherited Signal Connections

In Virtuoso Schematic Editor, an inherited signal connection is created by associating a net expression with the wire that represents the signal. The net expression acts like a wire name; that is, in the same manner that a wire name specifies the name of the net, the default name in the net expression specifies the name of the underlying net.

The AMS netlister translates inherited connection net expressions into net attributes that become part of the Verilog-AMS netlist. The translation of the net expression in the schematic, which has the form

[@property_name:%:default_net_name]*

occurs in accordance with the following syntax:

inh_conn_net_exp_declaration ::=

wire net_exp_attribute_list net_identifier;

net_exp_attribute_list ::=

(* integer inh_conn_prop_name = property_name; integer inh_conn_def_value = default_net_name; *)

property_name ::= string

default_net_name ::= string

For example, the AMS netlister translates the CDBA inherited connection net expression

[@xground:%:vdd!]*

into the following code in the Verilog-AMS netlist:

wire

(* integer inh_conn_prop_name="xground";

integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;

Virtuoso AMS Environment User Guide

Netlisting

Inherited Terminal Connections

In Virtuoso Schematic Editor, an inherited terminal connection is created by associating a net expression with the pin that physically represents the terminal. The pin can exist in a schematic, a layout, or schematicSymbol cellview.

The AMS netlister translates inherited terminal connection expressions into port attributes that become part of the Verilog-AMS netlist. The port attributes use the same syntax as net attributes. The only difference is that port attributes are attached to port declarations rather than net declarations.

Instance Values for Inherited Connections

In the Virtuoso Schematic Editor, you can override the default name associated with an inherited connection by creating or modifying the appropriate netSet property name and value pair on the component instance that represents the branch of the hierarchy that is affected. The AMS netlister translates netSet properties into cds_net_set attributes, which are stored in the Verilog-AMS netlist.

Then, when the elaborator encounters a net or port inherited connection attribute, it searches the hierarchy for a cds_net_set attribute that lists the inherited connection property name. If it finds the property name, the elaborator connects the net or terminal to the signal name specified in thecds_net_set attribute as the value of the property. If the elaborator cannot

find the property, it uses the default connection.

The CDBA netSet properties are represented, in Verilog-AMS netlists, as cds_net_set attributes. The syntax is:

cds_net_set_declaration ::=

module_identifier net_set_attribute_list instance_identifier (port_list_connection);

net_set_attribute_list ::=

(* integer cds_net_set[0:n] = { property_name {,property_name} }; property_list *)

property_list ::=

property_declaration; {property_declaration;}

property_declaration ::= simple_property

| inh_conn_expression

simple_property ::=

property_name = property_value

inh_conn_expression ::=

integer property_name[0:1] = { property_name, def_net_name }

n ::=

positive_integer

Virtuoso AMS Environment User Guide

Netlisting

property_name ::= string

property_value ::= string

def_net_name ::= string

The cds_net_set attribute is an array of one or more elements that stores the names of the netSet properties. Each element in the array has a corresponding property_name attribute.

In most cases, the property_value is a string specifying the override connection. The property_value can also be an inherited connection expression. In this case, the property_name is represented as a two-element array, using the first element as the new property name and the second element as the new default connection name. For example, consider the following CDBA netSet properties and values.

Property Value

xground [@new_ground:%:gnd5!]

These translate to the following cds_net_set attributes in the Verilog-AMS netlist:

comparator

(* integer library_binding = "amslib";

integer cds_net_set[0:1]= {"xground","vdd"};

integer xground[0:1] = {"new_ground","cds_globals.\\gnd5! "}; integer vdd = "cds_globals.\\3.3v! "; *)

I2 ( .inn( dacOut ), .inp( holdSig ), .out( compOut ) );

Third-Party Tools and Other Cadence Tools

The attributes added to netlists by the AMS netlister are Cadence-specific extensions to the Verilog-AMS language. As a consequence, some third-party tools and some Cadence tools, such as Verilog-XL, interpret the attributes as illegal code so parsing fails. To make sure that the Verilog-AMS netlist that is generated by the AMS netlister can be read by other tools, select the Netlister – Verilog-AMS category of the AMS options and turn on Conditionally include language extensions. This option encloses the cds_net_set attributes in compiler directives so the attributes are used only when the netlist is compiled by the AMS netlister.

For example, with Conditionally include language extensions turned on, the previous cds_net_set attributes are written to the netlist as follows.

comparator ‘ifdef INCA