- •CONTENTS
- •FIGURES
- •TABLES
- •1.1 Manual Contents
- •1.2 Notational Conventions and Terminology
- •1.3 Related Documents
- •1.4 Application Support Services
- •2.1 Typical Applications
- •2.2 Microcontroller Features
- •2.3 Functional Overview
- •2.3.1 Core
- •2.3.1.3 Register File
- •2.3.2 Memory Controller
- •2.4 Internal Timing
- •2.4.1 Clock and Power Management Logic
- •2.4.2 Internal Timing
- •2.4.2.1 Clock Failure Detection Logic
- •2.4.2.2 External Timing
- •2.4.2.3 Power Management Options
- •2.4.3 Internal Memory
- •2.4.4 Serial Debug Unit
- •2.4.5 Interrupt Service
- •2.5 Internal Peripherals
- •2.5.1 I/O Ports
- •2.5.2 Serial I/O (SIO) Port
- •2.5.3 Synchronous Serial I/O (SSIO) Port
- •2.5.4 Event Processor Array (EPA) and Timer/Counters
- •2.5.7 Stack Overflow Module
- •2.5.8 Watchdog Timer
- •2.6 Special Operating Modes
- •2.7 Chip Configuration Registers
- •3.1 Overview of the Instruction Set
- •3.1.1 BIT Operands
- •3.1.2 BYTE Operands
- •3.1.4 WORD Operands
- •3.1.5 INTEGER Operands
- •3.1.9 Converting Operands
- •3.1.10 Conditional Jumps
- •3.1.11 Floating-Point Operations
- •3.1.12 Extended Instructions
- •3.2 Addressing Modes
- •3.2.1 Direct Addressing
- •3.2.2 Immediate Addressing
- •3.2.3 Indirect Addressing
- •3.2.3.1 Extended Indirect Addressing
- •3.2.3.2 Indirect Addressing with Autoincrement
- •3.2.3.3 Extended Indirect Addressing with Autoincrement
- •3.2.3.4 Indirect Addressing with the Stack Pointer
- •3.2.4 Indexed Addressing
- •3.2.4.3 Extended Indexed Addressing
- •3.2.4.4 Zero-indexed Addressing
- •3.3 Considerations for Crossing Page Boundaries
- •3.4 Software Protection Features and Guidelines
- •4.1 Memory Map Overview
- •4.2 Memory Partitions
- •4.2.1 External Memory
- •4.2.2 Internal ROM
- •4.2.2.1 Program Memory in Page FFH
- •4.2.2.3 Reserved Memory Locations
- •4.2.2.4 Interrupt, PIH, and PTS Vectors
- •4.2.2.5 Chip Configuration Bytes
- •4.2.3 Internal RAM (Code RAM)
- •4.2.4.2 Peripheral SFRs
- •4.2.5 Register File
- •4.2.5.2 Stack Pointer (SP)
- •4.3 Windowing
- •4.3.1 Selecting a Window
- •4.3.2 Addressing a Location Through a Window
- •4.3.2.4 Unsupported Locations Windowing Example
- •4.3.2.5 Using the Linker Locator to Set Up a Window
- •4.3.3 Windowing and Addressing Modes
- •4.4 Controlling Read Access to the Internal ROM
- •4.5 Remapping Internal ROM
- •5.1 Functional Overview
- •5.2 Stack Operations
- •5.3 Stack Overflow Module Registers
- •5.4 Programming the Stack Overflow Module
- •5.4.1 Initializing the Stack Pointer
- •5.4.2 Enabling the Stack Overflow Module and Specifying Stack Boundaries
- •6.1 Overview of the Interrupt Control Circuitry
- •6.2 Interrupt Signals and Registers
- •6.3 Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1 PIH Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1.1 Using Software to Provide the Vector Address
- •6.3.1.2 Providing the Vector Address in Response to a CPU Request
- •6.3.2 Special Interrupts
- •6.3.2.1 Unimplemented Opcode
- •6.3.2.2 Software Trap
- •6.3.2.4 Stack Overflow
- •6.3.3 External Interrupt Signal
- •6.3.4 Shared Interrupt Requests
- •6.4 Interrupt Latency
- •6.4.1 Situations that Increase Interrupt Latency
- •6.4.2 Calculating Latency
- •6.4.2.2 PTS Interrupt Latency
- •6.5 Programming the Interrupts
- •6.5.1 Modifying Interrupt Priorities
- •6.5.2 Determining the Source of an Interrupt
- •6.6 Initializing the PTS Control Blocks
- •6.6.1 Specifying the PTS Count
- •6.6.2 Selecting the PTS Mode
- •6.6.3 Single Transfer Mode
- •6.6.4 Block Transfer Mode
- •6.6.5 Dummy Mode
- •7.1 I/O Ports Overview
- •7.2 Configuring the Port Pins
- •7.2.2 Configuring Ports 3 and 4 (Address/Data Bus)
- •7.2.3 Port Configuration Example
- •7.3.1 Address and Data Signals (Ports 3, 4, and EPORT)
- •7.3.1.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
- •7.3.5 External Interrupt Signal (Port 2)
- •7.3.6 PWM Signals (Port 11)
- •7.3.7 Serial I/O Port Signals (Ports 2 and 7)
- •7.3.8 Special Operating Mode Signal (Port 5 Pin 7)
- •7.3.9 Synchronous Serial I/O Port Signals (Port 10)
- •7.4 I/O Port Internal Structures
- •7.4.3 Internal Structure for Ports 3 and 4 (Address/Data Bus)
- •8.1 Serial I/O (SIO) Port Functional Overview
- •8.2 Serial I/O Port Signals and Registers
- •8.3 Serial Port Modes
- •8.3.1 Synchronous Mode (Mode 0)
- •8.3.2 Asynchronous Modes (Modes 1, 2, and 3)
- •8.3.2.1 Mode 1
- •8.3.2.2 Mode 2
- •8.3.2.3 Mode 3
- •8.3.2.4 Multiprocessor Communications
- •8.4 Programming the Serial Port
- •8.4.1 Configuring the Serial Port Pins
- •8.4.2 Programming the Control Register
- •8.4.3 Programming the Baud Rate and Clock Source
- •8.4.4 Enabling the Serial Port Interrupts
- •8.4.5 Determining Serial Port Status
- •CHAPTER 9 Synchronous Serial I/O (SSIO) Port
- •9.1 SSIO Port Overview
- •9.1.1 Standard Mode
- •9.1.2 Duplex Mode
- •9.2 SSIO pORT sIGNALS AND rEGISTERS
- •9.3 ssio Port Operation
- •9.3.1 Transmitting and Receiving Data
- •9.3.1.1 Normal Transfers (All Modes)
- •9.3.1.2 Handshaking Transfers (Standard Mode Only)
- •9.4 Programming the SSIO Port
- •9.4.1 Configuring the SSIO Port Pins
- •9.4.2 Configuring the SSIO Registers
- •9.4.2.1 The SSIO Baud (SSIO_BAUD) Register
- •9.4.2.3 The SSIO 0 Clock (SSIO0_CLK) Register
- •9.4.2.4 The SSIO 1 Clock (SSIO1_CLK) Register
- •9.4.3 Enabling the SSIO Interrupts
- •9.5 Programming Considerations
- •9.5.2 Standard Mode Considerations
- •9.5.3 Duplex Mode Considerations
- •10.1 PWM FUNCTIONAL OVERVIEW
- •10.2 PWM Signals and Registers
- •10.3 pwm operation
- •10.4 Programming the Frequency and Period
- •10.5 Programming the Duty Cycle
- •10.5.1 Sample Calculations
- •10.5.2 Reading the Current Value of the Down-counter
- •10.5.3 Enabling the PWM Outputs
- •10.5.4 Generating Analog Outputs
- •11.1 EPA Functional Overview
- •11.2 EPA and Timer/Counter Signals and Registers
- •11.3 Timer/Counter Functional Overview
- •11.3.1 Timer Multiplexing on the Time Bus
- •11.4 EPA Channel Functional Overview
- •11.4.1 Operating in Input Capture Mode
- •11.4.2 Operating in Output Compare Mode
- •11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels
- •11.4.4 Generating a 32-bit Time Value
- •11.4.5 Controlling a Pair of Adjacent Pins
- •11.5 Programming the EPA and Timer/Counters
- •11.5.1 Configuring the EPA and Timer/Counter Signals
- •11.5.2 Programming the Timers
- •11.5.3 Programming the Capture/Compare Channels
- •11.5.4 Programming the Compare-only (Output/Simulcapture) Channels
- •11.6 Enabling the EPA Interrupts
- •11.7 Determining Event Status
- •CHAPTER 12 Analog-to-digital (A/D) Converter
- •12.1 A/D Converter Functional Overview
- •12.2 A/D Converter Signals and Registers
- •12.3 A/D Converter Operation
- •12.4 Programming the A/D Converter
- •12.4.1 Programming the A/D Test Register
- •12.4.2 Programming the A/D Result Register (for Threshold Detection Only)
- •12.4.3 Programming the A/D Time Register
- •12.4.4 Programming the A/D Command Register
- •12.4.5 Programming the A/D Scan Register
- •12.4.6 Enabling the A/D Interrupt
- •12.5 Determining A/D Status and Conversion Results
- •12.6 Design Considerations
- •12.6.1 Designing External Interface Circuitry
- •12.6.1.1 Minimizing the Effect of High Input Source Resistance
- •12.6.1.2 Suggested A/D Input Circuit
- •12.6.1.3 Analog Ground and Reference Voltages
- •12.6.2 Understanding A/D Conversion Errors
- •CHAPTER 13 Minimum Hardware Considerations
- •13.1 Minimum Connections
- •13.1.1 Unused Inputs
- •13.1.2 I/O Port Pin Connections
- •13.2 Applying and Removing Power
- •13.3 Noise Protection Tips
- •13.4 The On-chip Oscillator Circuitry
- •13.5 Using an External Clock Source
- •13.6 Resetting the Microcontroller
- •13.6.1 Generating an External Reset
- •13.6.2 Issuing the Reset (RST) Instruction
- •13.6.3 Issuing an Illegal IDLPD Key Operand
- •13.6.4 Enabling the Watchdog Timer
- •13.6.5 Detecting Clock Failure
- •13.7 Identifying the Reset Source
- •14.1 Special Operating Mode Signals and Registers
- •14.2 Reducing Power Consumption
- •14.3 Idle Mode
- •14.3.1 Enabling and Disabling Idle Mode
- •14.3.2 Entering and Exiting Idle Mode
- •14.4 Powerdown Mode
- •14.4.1 Enabling and Disabling Powerdown Mode
- •14.4.2 Entering Powerdown Mode
- •14.4.3 Exiting Powerdown Mode
- •14.4.3.1 Generating a Hardware Reset
- •14.4.3.2 Asserting the External Interrupt Signal
- •14.4.3.3 Selecting an External Capacitor
- •14.5 ONCE Mode
- •CHAPTER 15 Interfacing with External Memory
- •15.1 Internal and External Addresses
- •15.2 External Memory Interface Signals and Registers
- •15.3 The Chip-select Unit
- •15.3.1 Defining Chip-select Address Ranges
- •15.3.2 Controlling Bus Parameters
- •15.3.3 Chip-select Unit Initial Conditions
- •15.3.4 Programming the Chip-select Registers
- •15.3.5 Example of a Chip-select Setup
- •15.4 Chip Configuration Registers and Chip Configuration Bytes
- •15.5 Bus Width and Multiplexing
- •15.5.1 A 16-bit Example System
- •15.5.2 16-bit Bus Timings
- •15.5.3 8-bit Bus Timings
- •15.5.4 Comparison of Multiplexed and Demultiplexed Buses
- •15.6 Wait States (Ready Control)
- •15.7 Bus-hold Protocol
- •15.7.1 Enabling the Bus-hold Protocol
- •15.7.2 Disabling the Bus-hold Protocol
- •15.7.3 Hold Latency
- •15.7.4 Regaining Bus Control
- •15.8 Write-control Modes
- •15.9 System Bus AC Timing Specifications
- •15.9.1 Deferred Bus-cycle Mode
- •15.9.2 Explanation of AC Symbols
- •15.9.3 AC Timing Definitions
- •16.1 Serial Debug Unit (SDU) Functional Overview
- •16.2 SDU Signals and Registers
- •16.3 SDU Operation
- •16.3.1 SDU State Machine
- •16.3.2 Code RAM Access State Machine
- •16.3.3 Minimizing Latency
- •16.4 Code RAM Access
- •16.4.1 Code RAM Data Transfer
- •16.4.2 Code RAM Access Instructions
- •16.4.3 Code RAM Data Transfer Example
- •16.5 SDU Interface Connector
- •17.1 Signals and Registers
- •17.2 Memory Protection Options
- •17.3 Entering Test-ROM Routines
- •17.3.1 Power-up and Power-down Sequences
- •17.4 ROM-dump Routine and Circuit
- •17.5 Serial Port Mode Routine
- •17.5.1 Serial Port RISM
- •17.5.2 Serial Port Mode Circuit
- •17.6 SDU RISM Execution Routine
- •17.6.1 SDU RISM Data Transfer
- •17.6.1.1 SDU RISM Data Transfer Before
- •17.6.1.2 SDU RISM Data Transfer After
- •17.6.2 SDU RISM Execution Circuit
- •17.7 RISM Command Descriptions
- •17.8 Executing Programs from Register RAM
- •17.9 RISM Command Examples
- •17.9.1 Serial Port Mode RISM Read Command Example
- •17.9.2 Serial Port Mode RISM Write Command Example
- •17.9.3 SDU RISM Execution Write Command Example
- •17.9.4 SDU RISM Execution Go Command Example
- •B.1 Functional Groupings of Signals
- •B.2 Signal Descriptions
- •B.3 Default Conditions
CHAPTER 14
SPECIAL OPERATING MODES
The 8XC196EA has two power saving modes: idle and powerdown. It also has an on-circuit emulation (ONCE) mode that electrically isolates the microcontroller from the other system components. This chapter describes each mode and explains how to enter and exit them.
14.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS
Table 14-1 lists the signals and Table 14-2 lists the registers that are mentioned in this chapter.
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Table 14-1. Operating Mode Control Signals |
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Type |
Description |
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CLKOUT |
O |
Clock Output |
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Output of the internal clock generator. You can select one of five frequencies: f, f/2, |
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f/4, f/8, or f/16. CLKOUT has a 50% duty cycle. |
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CLKOUT shares a package pin with P2.7 |
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EXTINT |
I |
External Interrupt |
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In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt |
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pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high |
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time is one state time. |
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In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the |
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device to resume normal operation. The interrupt does not need to be enabled, but |
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the pin must be configured as a special-function input. If the EXTINT interrupt is |
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enabled, the CPU executes the interrupt service routine. Otherwise, the CPU |
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executes the instruction that immediately follows the command that invoked the |
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power-saving mode. |
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In idle mode, asserting any enabled interrupt causes the device to resume normal |
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operation. |
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EXTINT shares a package pin with P2.2. |
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ONCE# |
I |
On-circuit Emulation |
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Holding ONCE# low during the rising edge of RESET# places the device into on- |
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circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, |
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thereby isolating the microcontroller from other components in the system. The |
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value of ONCE# is latched when the RESET# pin goes inactive. While the device is |
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in ONCE mode, you can debug the system using a clip-on emulator. |
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To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To |
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prevent inadvertent entry into ONCE mode, either configure this pin as an output or |
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hold it high during reset and ensure that your system meets the VIH specification. |
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ONCE# shares a package pin with P2.6 and HLDA#. |
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PLLEN |
I |
Phase-locked Loop Enable |
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This active-high input pin enables the on-chip clock multiplier. |
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14-1
8XC196EA USER’S MANUAL
Table 14-1. Operating Mode Control Signals (Continued)
Signal |
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Description |
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RESET# |
I/O |
Reset |
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A level-sensitive reset input to, and an open-drain system reset output from, the |
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microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull- |
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down transistor connected to the RESET# pin for 16 state times. In the powerdown |
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and idle modes, asserting RESET# causes the microcontroller to reset and return to |
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normal operating mode. After a reset, the first instruction fetch is from FF2080H (or |
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1F2080H in external memory). |
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RPD |
I |
Return from Powerdown |
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Timing pin for the return-from-powerdown circuit. |
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If your application uses powerdown mode, connect a capacitor between RPD and |
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VSS if either of the following conditions are true. |
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• the internal oscillator is the clock source |
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• the phase-locked loop (PLL) circuitry is enabled (see PLLEN signal description) |
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The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize |
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before the internal CPU and peripheral clocks are enabled. |
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The capacitor is not required if your application uses powerdown mode and if both |
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of the following conditions are true. |
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• an external clock input is the clock source |
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• the phase-locked loop circuitry is disabled |
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If your application does not use powerdown mode, leave this pin unconnected. |
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RPD shares a package pin with P5.7. |
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TMODE# |
I |
Test-Mode Entry |
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If this pin is held low during reset, the microcontroller will enter a test mode. The |
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value of several other pins defines the actual test mode. All test modes, except |
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TROM execution, are reserved for Intel factory use. If you choose to configure this |
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signal as an input, always hold it high during reset and ensure that your system |
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meets the VIH specification to prevent inadvertent entry into test mode. |
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TMODE# shares a package pin with P5.4 and BREQ#. |
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14-2
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SPECIAL OPERATING MODES |
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Table 14-2. Operating Mode Control and Status Registers |
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Mnemonic |
Address |
Description |
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CCR0 |
2018H |
Chip Configuration 0 |
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Enables or disables the IDLPD #1 and IDLPD #2 instructions. |
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When enabled, the IDLPD #1 instruction causes the microcontrol- |
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ler to enter idle mode and the IDLPD #2 instruction causes the |
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microcontroller to enter powerdown mode. This register also |
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selects the write-control mode and contains the bus-control |
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parameters for fetching chip configuration byte 1. |
INT_MASK |
0008H |
Interrupt Mask |
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Bit 6 of this register enables and disables (masks) external |
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interrupt EXTINT. |
INT_PEND |
0009H |
Interrupt Pending |
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Bit 6 of this register is set to indicate pending external interrupt |
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EXTINT. |
P2_DIR |
1FD2H |
Port Direction Register |
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Each bit controls the configuration of the corresponding pin. |
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Clearing a bit configures a pin as a complementary output; setting |
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a bit configures a pin as a high-impedance input or an open-drain |
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output. |
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P2_MODE |
1FD0H |
Port Mode Register |
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Each bit controls the mode of the corresponding pin. Setting a bit |
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configures a pin as a special-function signal; clearing a bit |
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configures a pin as a general-purpose I/O signal. |
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P2_PIN |
1FD6H |
Port Pin Register |
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Each bit reflects the current state of the corresponding pin, |
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regardless of the pin’s mode and configuration. |
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P2_REG |
1FD4H |
Port Data Output Register |
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For I/O Mode (Px_MODE.x = 0) |
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When a port pin is configured as a complementary output |
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(Px_DIR.x = 0), setting the corresponding port data bit drives a |
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one on the pin, and clearing the corresponding port data bit |
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drives a zero on the pin. |
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When a port pin is configured as a high-impedance input or an |
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open-drain output (Px_DIR.x = 1), clearing the corresponding |
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port data bit drives a zero on the pin, and setting the corre- |
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sponding port data bit floats the pin, making it available as a |
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high-impedance input. |
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For Special-function Mode (Px_MODE.x = 1) |
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When a port pin is configured as an output (either comple- |
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mentary or open-drain), the corresponding port data bit value |
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is immaterial because the corresponding on-chip peripheral or |
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system function controls the pin. |
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To configure a pin as a high-impedance input, set both the |
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Px_DIR and Px_REG bits. |
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14-3
8XC196EA USER’S MANUAL
14.2 REDUCING POWER CONSUMPTION
Both power-saving modes conserve power by disabling portions of the internal clock circuitry (Figure 14-1). The remainder of this section describes both power-saving modes in detail.
FXTAL1
XTAL1
XTAL2
Disable Oscillator (Powerdown)
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Disable |
Phase |
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Filter |
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PLL |
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Comparator |
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(Powerdown) |
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Phase-locked |
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Oscillator |
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XTAL1 |
XTAL1 |
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PLLEN |
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Phase-locked Loop |
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Clock Multiplier |
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F |
2F |
1 |
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0
f
Disable Clock Input (Powerdown)
Divide by two
Circuit
f/2 |
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To reset logic |
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Disable Clocks (Idle, Powerdown) |
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Clock |
Clock |
CPU Clocks (PH1, PH2) |
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Failure |
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Generators |
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Detection |
Peripheral Clocks (PH1, PH2) |
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f/2 |
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Programmable |
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OSC |
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Divider |
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(CLK1:0) |
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0 |
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f |
CLKOUT |
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1 |
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Disable Clocks (Powerdown) |
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A3378-01 |
Figure 14-1. Clock Control During Power-saving Modes
14-4