2.6SPECIAL OPERATING MODES

7

0

LOC

1

WS1

WS0

DEMUX

BHE#

BW16

PD

Bit

Bit

Function

Number

Mnemonic

7

LOC

Lock Bit

This bit controls read access to the ROM during normal operation.

0 = read protect

1 = no protection

Refer to “Controlling Read Access to the Internal ROM” on page 4-26 for

details.

6

1

To guarantee proper operation, write one to this bit.

CCR0 (Continued)

no direct access†

7

0

LOC

1

WS1

WS0

DEMUX

BHE#

BW16

PD

Bit

Bit

Function

Number

Mnemonic

5:4

WS1:0

Wait States

These bits, along with the READY pin, control the number of wait states

that are used for an external fetch of chip configuration byte 1 (CCB1).

WS1 WS0

0

0

zero wait states

0

1

one wait state

1

0

two wait states

1

1

three wait states

If READY is low when this number is reached, additional wait states are

added until READY is pulled high.

3

DEMUX

Select Demultiplexed Bus

Selects the demultiplexed bus mode for an external fetch of CCB1:

0

= multiplexed — address and data are multiplexed on AD15:0.

1

= demultiplexed — data only on AD15:0.

2

BHE#

Write-control Mode

Selects the write-control mode, which determines the functions of the

BHE#/WRH# and WR#/WRL# pins for external bus cycles:

0

= write strobe mode: the BHE#/WRH# pin operates as WRH#, and the

WR#/WRL# pin operates as WRL#.

1

= standard write-control mode: the BHE#/WRH# pin operates as

BHE#, and the WR#/WRL# pin operates as WR#.

CCR0 (Continued)

no direct access†

7

0

LOC

1

WS1

WS0

DEMUX

BHE#

BW16

PD

Bit

Bit

Function

Number

Mnemonic

1

BW16

Buswidth Control

Selects the bus width for an external fetch of CCB1:

0 = 8-bit bus

1 = 16-bit bus

0

PD

Powerdown Enable

Enables or disables the IDLPD #1 and IDLPD #2 instructions. When

enabled, the IDLPD #1 instruction causes the microcontroller to enter idle

mode and the IDLPD #2 instruction causes the microcontroller to enter

powerdown mode.

0 = disable idle and powerdown modes

1 = enable idle and powerdown modes

If your design uses idle or powerdown mode, set this bit when you

program the CCBs. If it does not, clearing this bit when you program the

CCBs will prevent accidental entry into idle or powerdown mode.

(Chapter 14, “Special Operating Modes,” discusses idle and powerdown

modes.)

CCR1

no direct access†

7

0

1

CFD

DM

0

WDD

REMAP

MODE64

0

Bit

Bit

Function

Number

Mnemonic

7

1

To guarantee proper operation, write one to this bit.

6

CFD

Clock-failure Detection

This bit enables or disables the clock failure detection circuitry.

0

= disables clock-failure detection circuitry

1

= enables clock-failure detection circuitry

(See “Clock Failure Detection Logic” on page 2-12.)

5

DM

Deferred Mode

Enables the deferred bus-cycle mode. If the microcontroller is using a

demultiplexed bus and deferred mode is enabled, a delay of 2t occurs in

the first bus cycle following a chip-select output change, the first write

cycle following a read cycle, and the first read cycle following a write

cycle. (See “Deferred Bus-cycle Mode” on page 15-41.)

0

= deferred bus-cycle mode disabled

1

= deferred bus-cycle mode enabled

4

To guarantee proper operation, write zero to this bit.

3

WDD

Watchdog Timer Disable

Selects whether the watchdog timer is always enabled or disabled until

the first time it is cleared. If this bit is clear, the watchdog is enabled at

reset, so software must clear the watchdog within 64K state times to

prevent another reset. If this bit is set, the watchdog is disabled until the

first time you clear it. (See “Enabling the Watchdog Timer” on page

13-12.)

0

= always enabled

1

= disabled at reset; enabled the first time it is cleared

CCR1 (Continued)

no direct access†

7

0

1

CFD

DM

0

WDD

REMAP

MODE64

0

Bit

Bit

Function

Number

Mnemonic

2

REMAP

Internal ROM Mapping

The EA# pin controls whether accesses to FF2000–FF3FFFH are

directed to internal ROM or to external memory. When EA# is low

(external execution), REMAP is ignored. When EA# is high (internal

execution), REMAP controls whether the upper 7-Kbyte area (FF2400–

FF3FFFH) of internal ROM is mapped only into page FFH or into both

pages FFH and 00H.

0 = ROM maps to page FFH only

1 = ROM maps to page FFH and page 00H

(See “Remapping Internal ROM” on page 4-29.)

1

MODE64

Addressing Mode

Selects 64-Kbyte or 2-Mbyte addressing.

0 = selects 2-Mbyte addressing

1 = selects 64-Kbyte addressing

In 2-Mbyte mode, code can execute from almost anywhere in the

address space. In 64-Kbyte mode, code can execute only from page

FFH. (See “Fetching Code and Data in the 2-Mbyte and 64-Kbyte Modes”

on page 4-31 for more information.)

0

0

Reserved; for compatibility with future devices, write zero to this bit.