8XC196EA USER’S MANUAL

12.6.1 Designing External Interface Circuitry

The external interface circuitry to an analog input is highly dependent upon the application and can affect the converter characteristics. Factors such as input pin leakage, sample capacitor size, and multiplexer series resistance from the input pin to the sample capacitor must be considered in the external circuit’s design. These factors are idealized in Figure 12-9.

Figure 12-9. Idealized A/D Sampling Circuitry

During the sample window, the external input circuit must be able to charge the sample capacitor

(CS) through the series combination of the input source resistance (RSOURCE), the input series resistance (R1), and the comparator feedback resistance (RF). The total effective series resistance

(RT) is calculated using the following formula, where AV is the gain of the comparator circuit.

RF

RT = RSOURCE + R1 + ----------------

AV + 1

Typically, the (RF / AV + 1) term is the major contributor to the total resistance and the factor that determines the minimum sample time specified in the datasheet.

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ANALOG-TO-DIGITAL (A/D) CONVERTER

12.6.1.1Minimizing the Effect of High Input Source Resistance

Under some conditions, the input source resistance (RSOURCE) can be great enough to affect the measurement. You can minimize this effect by increasing the sample time or by connecting an

external capacitor (CEXT) from the input pin to ANGND. The external signal will charge CEXT to the source voltage level. When the channel is sampled, CEXT acts as a low-impedance source to charge the sample capacitor (CS). A small portion of the charge in CEXT is transferred to CS, resulting in a drop of the sampled voltage. The voltage drop is calculated using the following formula.

CEXT + CS

If CEXT is 0.005 µF or greater, the error will be less than –0.4 LSB in 10-bit conversion mode. The

use of CEXT in conjunction with RSOURCE forms a low-pass filter that reduces noise input to the A/D converter.

High RSOURCE resistance can also cause errors due to the input leakage (ILI1). ILI1 is typically much lower than its specified maximum (consult the datasheet for specifications). The combined effect

of ILI1 leakage and high RSOURCE resistance is calculated using the following formula.

External circuits with RSOURCE resistance of 1 kΩ or lower and VREF equal to 5.0 volts will have a resultant error due to source impedance of 0.6 LSB or less.

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8XC196EA USER’S MANUAL

12.6.1.2Suggested A/D Input Circuit

The suggested A/D input circuit shown in Figure 12-10 provides limited protection against overvoltage conditions on the analog input. Should the input voltage be driven significantly below ANGND or above VREF, diode D2 or D1 will forward bias at about 0.8 volts. The device’s input protection begins to turn on at approximately 0.5 volts beyond ANGND or VREF. The 270Ω resistor limits the current input to the analog input pin to a safe value, less than 1 mA.

NOTE

Driving any analog input more than 0.5 volts beyond ANGND or VREF begins to activate the input protection devices. This drives current into the internal reference circuitry and substantially degrades the accuracy of A/D conversions on all channels.

Figure 12-10. Suggested A/D Input Circuit

12.6.1.3Analog Ground and Reference Voltages

Reference supply levels strongly influence the absolute accuracy of the conversion. For this reason, we recommend that you tie the ANGND pin to the VSS pin as close to the device as possible, using a minimum trace length. In a noisy environment, we highly recommend the use of a separate analog ground plane that connects to VSS at a single point as close to the device as possible. IREF may vary between 2 mA and 5 mA during a conversion. To minimize the effect of this fluctuation, mount a 1.0 µF ceramic or tantalum bypass capacitor between V REF and ANGND, as close to the device as possible.

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