8XC196EA USER’S MANUAL

6.3.2.2Software Trap

The TRAP instruction (opcode F7H) causes an interrupt call that is vectored through location FF2010H (default). This interrupt is useful when debugging software or generating software interrupts. When the TRAP instruction generates the interrupt, no other interrupt request can be acknowledged until after the next instruction executes.

6.3.2.3NMI

The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt routines. NMI has a higher priority than all the prioritized interrupts. (Only the unimplemented opcode and software trap interrupts have higher priority.) It is passed directly from the transition detector to the priority resolver, and it vectors indirectly through location FF203EH.The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally. Because interrupts are edgetriggered, only one interrupt is generated, even if the pin is held high.

If your system does not use the NMI interrupt, connect the NMI pin to VSS to prevent spurious interrupts.

6.3.2.4Stack Overflow

The stack overflow module monitors the value of the stack pointer (SP) and generates a nonmaskable interrupt request if the value is outside the boundaries you specify. This module helps to ensure data integrity. Without the stack overflow module, the stack could grow too large and corrupt other data, causing a fatal system error.

If an overflow occurs, the stack overflow module sets the stack overflow interrupt pending bit in INT_PEND1. Your interrupt service routine must write to the STACK_TOP register to re-enable the overflow detection circuitry. Otherwise, the stack overflow module is unable to signal another overflow. Chapter 5, “Stack Overflow Module,” describes the stack overflow module in detail.

6.3.3External Interrupt Signal

A momentary spike on the EXTINT pin may be interpreted as an interrupt request. To prevent this type of erroneous interrupt, hold EXTINT low when it is inactive.

6.3.4Shared Interrupt Requests

The event processor array can generate many individual interrupt requests. To accommodate all EPA interrupt sources, two peripheral interrupt handlers (PIHs) were incorporated into the 8XC196EA. Each PIH handles 16 individual interrupt requests; each can be programmed to request service from either the interrupt controller or the PTS.

In addition, a capture overrun on EPA capture/compare channels 3–16 sets the interrupt pending bit for the EPAx_OVR interrupt. When the CPU receives an EPAx_OVR interrupt request, it cannot determine which channel had the overrun.

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