SYNCHRONOUS SERIAL I/O (SSIO) PORT
9.2SSIO PORT SIGNALS AND REGISTERS
Table 9-1 and Table 9-2 describe the signals and registers associated with the SSIO port.
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Table 9-1. SSIO Port Signals |
Signal |
Type |
Description |
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CHS# |
I |
Channel Select |
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This signal is available only when the SSIO is configured for channel-select |
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operation. The function of the signal depends on whether the SSIO is |
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configured as master or slave. When the SSIO is configured as a slave, an |
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external master activates CHS# to communicate with the SSIO. When the |
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SSIO is configured as a master, an external master activates CHS# when it |
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wants the SSIO to give up the bus. |
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CHS# shares a package pin with P10.2. |
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SC0 |
I/O |
Serial Clock x |
SC1 |
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In standard mode, SC0 is the serial clock pin for channel 0 and SC1 is the |
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serial clock pin for channel 1. In duplex and channel-select modes, SC0 is |
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the serial clock pin for both channels 0 and 1 and SC1 is not available. |
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For normal transfers, configure SCx as either a complementary output |
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signal (for master) or a high-impedance input signal (for slave). When |
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channel x is configured as a master, the serial clock is output on SCx. |
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During transfers, the SCx output signal is synchronized with the baud clock; |
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between transfers, the SSIO drives SCx to its idle state. When channel x is |
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configured as a slave, the serial clock is input on SCx. |
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For handshaking transfers, configure SCx as an open-drain signal and use |
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an external pull-up resistor. Transfers are initiated only when SCx is high; |
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therefore, a slave device can pull SCx low when it is not ready. When |
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channel x is configured as a master, the serial clock is output on SCx. |
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During transfers, the SCx output signal is synchronized with the baud clock; |
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between transfers, the SSIO floats SCx. When channel x is configured as a |
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slave, the SSIO pulls SCx low when channel x’s buffer is empty for |
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transmissions or full for receptions; it floats SCx when channel x’s buffer is |
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full for transmissions and empty for receptions. |
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SC0 shares a package pin with P10.0, and SC1 shares a package pin with |
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P10.2. |
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SD0 |
I/O |
Serial Data x |
SD1 |
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This pin is the serial data pin for channel x. For transmissions, configure |
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SDx as a complementary output signal. For receptions, configure SDx as a |
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high-impedance input signal. |
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In standard mode, SD0 and SD1 can be configured for either transmissions |
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or receptions. In duplex mode, configure SD0 for transmissions and SD1 for |
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receptions. In channel-select half-duplex mode, configure SD1 for |
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transmissions or receptions. In channel-select full-duplex mode, configure |
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SD0 for transmissions and SD1 for receptions. |
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SD0 shares a package pin with P10.1, and SD1 shares a package pin with |
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P10.3. |
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9-5
8XC196EA USER’S MANUAL
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Table 9-2. SSIO Port Registers |
Mnemonic |
Address |
Description |
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INT_MASK1 |
0013H |
Interrupt Mask 1 |
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Use this register to enable or disable interrupts from the SSIO |
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channels. |
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As a transmitter, an SSIO channel generates an interrupt request when |
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its transmit buffer is empty. As a receiver, an SSIO channel generates |
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an interrupt request when its receive buffer is full. As a master, in |
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channel-select mode, the SSIO can generate an interrupt request |
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when another device takes control of the bus. In this case, the interrupt |
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request corresponds to the SSIO0 interrupt mask bit. |
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Setting the SSIO0 (INT_MASK1.0) bit of this register enables the SSIO |
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channel 0 transfer interrupt or the SSIO channel-select master |
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contention interrupt; clearing the bit disables (masks) the interrupt. |
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Setting the SSIO1 (INT_MASK1.1) bit of this register enables the SSIO |
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channel 1 transfer interrupt; clearing the bit disables (masks) the |
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interrupt. |
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INT_PEND1 |
0012H |
Interrupt Pending 1 |
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When set, SSIO0 (INT_PEND1.0) indicates a pending SSIO channel 0 |
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transfer interrupt or SSIO channel-select master contention interrupt. |
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When set, SSIO1 (INT_PEND1.1) indicates a pending channel 1 |
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transfer interrupt. |
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P10_DIR |
1FC3H |
Port 10 Direction |
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Each bit controls the configuration of the corresponding pin. Clearing a |
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bit configures the corresponding pin as a complementary output; |
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setting a bit configures the corresponding pin as an open-drain output |
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or high-impedance input. |
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Write to P10_DIR.0, P10_DIR.1, P10_DIR.2, and P10_DIR.3 to |
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configure SC0, SD0, SC1, and SD1. (See “Configuring the SSIO |
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Registers” on page 9-12.) |
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P10_MODE |
1FC1H |
Port 10 Mode |
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Each bit controls the mode of the corresponding pin. Setting a bit |
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configures a pin as a special-function signal; clearing a bit configures a |
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pin as a general-purpose I/O signal. |
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Set P10_MODE.0, P10_MODE.1, P10_MODE.2, and P10_MODE.3 to |
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configure pins P10.0, P10.1, P10.2, and P10.3 as SC0, SD0, SC1, and |
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SD1. (See “Configuring the SSIO Registers” on page 9-12.) |
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P10_PIN |
1FC7H |
Port 10 Pin |
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Each bit reflects the current state of the corresponding pin, regardless |
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of the pin’s mode and configuration. |
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9-6
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SYNCHRONOUS SERIAL I/O (SSIO) PORT |
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Table 9-2. SSIO Port Registers (Continued) |
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Mnemonic |
Address |
Description |
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P10_REG |
1FC5H |
Port 10 Data Output |
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For I/O Mode |
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When a port pin is configured as a complementary signal, setting |
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the corresponding port data bit drives a one on the pin and |
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clearing the corresponding port data bit drives a zero on the pin. |
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When a port pin is configured as an open-drain signal, clearing the |
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corresponding port data bit drives a zero on the pin and setting the |
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corresponding port data bit floats the pin, making it available as a |
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high-impedance input. |
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For Special-function Mode |
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When a port pin is configured as an output (either complementary |
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or open-drain) signal, the corresponding port data bit value is |
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immaterial because the corresponding on-chip peripheral or |
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system function controls the pin. |
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When a port pin is configured as an open-drain signal, setting the |
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corresponding port data bit floats the pin, making it available as a |
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high-impedance input. |
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Write to P10_REG.0, P10_REG.1, P10_REG.2, and P10_REG.3 to |
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configure SC0, SD0, SC1, and SD1. (See “Configuring the SSIO |
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Registers” on page 9-12.) |
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PTSSEL |
0004H |
PTS Select |
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Selects either a PTS microcode routine or a standard interrupt service |
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routine for the SSIOx interrupts. Setting the SSIO0 or SSIO1 bit |
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(PTSSEL.8 or PTSSEL.9) of this register selects a PTS microcode |
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routine; clearing the SSIOx bit selects a standard interrupt service |
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routine. |
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PTSSRV |
0006H |
PTS Service |
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Used by the hardware to indicate that the SSIOx interrupt has been |
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serviced by the PTS routine. |
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SSIO_BAUD |
1F94H |
SSIO Baud Rate |
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Enables the baud-rate generator and defines the baud rate for the |
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baud clock. |
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SSIO0_BUF |
1F90H |
SSIO x Receive and Transmit Buffers |
SSIO1_BUF |
1F92H |
Contains either received data or data for transmission, depending on |
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the channel configuration. Data is shifted into this register from the SDx |
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pin or from this register to the SDx pin, with the most-significant bit first. |
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SSIO0_CON |
1F91H |
SSIO x Control |
SSIO1_CON |
1F93H |
Configures the SSIO channel as either master or slave, transmitter or |
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receiver, selects the channel’s transfer type (normal or handshaking), |
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determines whether the SSIO enables or disables the channel at the |
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completion of a transfer, and indicates the buffer status and whether a |
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buffer error occurred in the last transfer. |
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9-7