8XC196EA USER’S MANUAL

The SSIO x buffer (SSIOx_BUF) register contains either data for transmission or data received, depending on channel x’s configuration. For transmissions, data is shifted from this register to the SDx pin; for receptions, data is sampled into this register from the SDx pin. For both transmissions and receptions, the data is transferred with most-significant bit first.

9.4.3Enabling the SSIO Interrupts

Each SSIO channel can generate an interrupt if you enable the individual interrupt as well as globally enabling servicing of all maskable interrupts. The INT_MASK1 register enables and disables individual interrupts. To enable the SSIO0 or SSIO1 interrupts, set the corresponding bits in INT_MASK1 (INT_MASK1.0 or INT_MASK1.1) and execute the EI instruction to globally enable interrupt servicing. For handshaking transfers, you can use the single-transfer PTS microcode interrupt routine to complete multi-byte transfers. In this case, set the SSIO0 or SSIO1 PTS interrupt bit (PTSSEL.8 or PTSSEL.9). See Chapter 6, “Standard and PTS Interrupts,” for more information about interrupts.

As a transmitter, SSIO channel x generates an SSIOx interrupt request when its transmit buffer is empty. As a receiver, SSIO channel x generates an SSIOx interrupt request when its receive buffer is full. As a master, in channel-select mode, the SSIO can generate a master contention interrupt request when the CHS# pin is externally activated. In this case, the interrupt request corresponds to the SSIO0 interrupt. SSIO1_CLK contains two bits associated with the master contention interrupt: an interrupt enable bit (CONINT) and an interrupt pending bit (CONPND). As a master, in channel-select mode, the SSIO always sets CONPND when the CHS# pin is externally activated. If CONINT is set, the SSIO sets the SSIO0 interrupt pending bit (INT_PEND1.0) along with CONPND when the CHS# pin is externally activated.

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