8XC196EA USER’S MANUAL

When the peripheral interrupt handler 1 detects an interrupt request, it sets the corresponding bit in the interrupt pending (PIH1_INT_PEND) register. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

Figure 6-18. PIH1 Interrupt Pending (PIH1_INT_PEND) Register

6.6INITIALIZING THE PTS CONTROL BLOCKS

Each PTS interrupt requires a block of data, in register RAM, called the PTS control block (PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up the specific parameters for the routine. You must set up the PTSCB for each interrupt source before enabling the corresponding PTS interrupts.

Store the address of the first (lowest) PTSCB byte in the PTS vector table in special-purpose memory (see “Special-purpose Memory in Page FFH” on page 4-7). Figure 6-19 shows the PTSCB for each PTS mode. Unused PTSCB bytes can be used as extra RAM.

NOTE

The PTSCB must be located in the internal register file. The location of the first byte of the PTSCB must be aligned on a quad-word boundary (an address evenly divisible by 8).

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STANDARD AND PTS INTERRUPTS

Figure 6-19. PTS Control Blocks

6.6.1Specifying the PTS Count

For single transfer, block transfer, and missed-event routines, the first location of the PTSCB contains an 8-bit value called PTSCOUNT. This value defines the number of interrupts that will be serviced by the PTS routine. The PTS decrements PTSCOUNT after each PTS cycle. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit (Figure 6-20), which requests an end-of-PTS interrupt. If PIHx_PTS is the interrupt source, then hardware also clears the corresponding PIHx_PTSSEL bit and sets the PIHx_PTSSRV bit (Figure 6-12 and “Windowing” on page 4-17).

The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appropriate PTSSEL and PIHx_PTSSEL bits to re-enable PTS interrupt service.

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