CHAPTER 7
I/O PORTS
The microcontroller contains one 5-bit I/O port, one 6-bit I/O port, and nine 8-bit I/O ports. Each port pin can function as a general-purpose I/O signal or as a special-function signal. General-pur- pose I/O signals provide a mechanism to transfer information between the microcontroller and the surrounding system circuitry. They can read system status, monitor system operation, output microcontroller status, configure system options, generate control signals, provide serial communication, and so on. Special-function signals are associated with on-chip peripherals or system functions.
7.1I/O PORTS OVERVIEW
Most port pins can serve as low-speed input/output signals (I/O mode) or as signals for peripheral and/or system functions (special-function mode). Each port pin can function as a complementary or open-drain signal. For complementary signals, the microcontroller drives a one or a zero on the pin. For open-drain signals, the microcontroller either floats the pin, making it available as a high impedance input, or pulls the pin low. Each port contains dedicated special-function registers (SFRs) that allow you to select a pin’s mode, configuration, and output value, and read a pin’s input value.
The microcontroller contains two port types: standard and memory mapped. The SFRs for standard I/O ports are located in the special-function address space. Using windowing, these registers are accessible with direct addressing. (See “Windowing” on page 4-17.) The SFRs for memorymapped I/O ports are located in the memory-mapped address space. Unlike standard I/O ports, memory-mapped I/O port registers are accessible only with indirect or indexed addressing; windowing is not available for memory-mapped I/O port registers.
For each port, Table 7-1 lists the number of pins, the port type, and the associated peripheral or system function.
7-1
8XC196EA USER’S MANUAL
Table 7-1. Microcontroller I/O Ports
Port |
Pins |
Type |
Associated Peripheral |
|
or System Function |
||||
|
|
|
||
|
|
|
|
|
Extended Port (EPORT) |
8 |
Memory mapped |
Extended address lines, chip-select unit |
|
|
|
|
|
|
Port 2 |
8 |
Standard |
SIO, interrupts, bus control, clock generation |
|
|
|
|
|
|
Port 3 |
8 |
Memory mapped |
Address/data bus |
|
|
|
|
|
|
Port 4 |
8 |
Memory mapped |
Address/data bus |
|
|
|
|
|
|
Port 5 |
8 |
Memory mapped |
Bus control |
|
|
|
|
|
|
Port 7 |
8 |
Standard |
EPA, SIO, timers |
|
|
|
|
|
|
Port 8 |
8 |
Standard |
EPA |
|
|
|
|
|
|
Port 9 |
8 |
Standard |
EPA |
|
|
|
|
|
|
Port 10 |
6 |
Standard |
EPA, SIO |
|
|
|
|
|
|
Port 11 |
8 |
Standard |
PWM |
|
|
|
|
|
|
Port 12 |
5 |
Memory mapped |
— |
|
|
|
|
|
For each port pin, Table 7-2 lists the I/O and special-function signal names, the special-function signal type, and the special-function signal’s associated peripheral or system function. For a description of a pin’s special-function signal, see “Using the Special-function Signals” on page 7-11.
7-2
I/O PORTS
Table 7-2. Microcontroller Port Signals
|
|
Special-function |
Special-function |
Special-function |
|
Port |
I/O Signal |
Signal Peripheral or |
|||
Signal |
Signal Type |
||||
|
|
System Function |
|||
|
|
|
|
||
|
|
|
|
|
|
Extended Port |
EPORT.0 |
A16 |
O |
Extended address bus |
|
|
EPORT.1 |
A17 |
O |
Extended address bus |
|
|
EPORT.2 |
A18 |
O |
Extended address bus |
|
|
EPORT.3 |
A19 |
O |
Extended address bus |
|
|
EPORT.4 |
A20 |
O |
Extended address bus |
|
|
EPORT.5 |
CS0# |
O |
Chip-select unit |
|
|
EPORT.6 |
CS1# |
O |
Chip-select unit |
|
|
EPORT.7 |
CS2# |
O |
Chip-select unit |
|
Port 2 |
P2.0 |
TXD0 |
O |
Serial I/O unit |
|
|
P2.1 |
RXD0 |
I/O |
Serial I/O unit |
|
|
P2.2 |
EXTINT |
I |
Interrupts |
|
|
P2.3 |
TXD1 |
O |
Bus controller |
|
|
P2.4 |
RXD1 |
/O |
Interrupts |
|
|
P2.5 |
HOLD# |
I |
Bus controller |
|
|
P2.6 |
HLDA#/ONCE# |
O |
Bus controller |
|
|
P2.7 |
CLKOUT |
O |
Clock generator |
|
Port 3 |
P3.7:0 |
AD7:0 |
I/O |
Address/data bus, low byte |
|
Port 4 |
P4.7:0 |
AD15:8 |
I/O |
Address/data bus, high byte |
|
Port 5 |
P5.0 |
ALE |
O |
Bus controller |
|
|
P5.1 |
INST |
O |
Bus controller |
|
|
P5.2 |
WR#/WRL# |
O |
Bus controller |
|
|
P5.3 |
RD# |
O |
Bus controller |
|
|
P5.4 |
BREQ# |
O |
Bus controller |
|
|
P5.5 |
BHE#/WRH# |
O |
Bus controller |
|
|
P5.6 |
READY |
I |
Bus controller |
|
|
P5.7 |
RPD |
I |
Powerdown |
|
Port 7 |
P7.0 |
EPA0/T1CLK |
I/O |
EPA, timer 1 |
|
|
P7.1 |
EPA1/T1RST |
I/O |
EPA, timer 1 |
|
|
P7.2 |
EPA2/T2CLK |
I/O |
EPA, timer 2 |
|
|
P7.3 |
EPA3/T2RST |
I/O |
EPA, timer 2 |
|
|
P7.4 |
EPA4/T3CLK |
I/O |
EPA, timer 3 |
|
|
P7.5 |
EPA5/T3RST |
I/O |
EPA, timer 3 |
|
|
P7.6 |
EPA6/T4CLK |
I/O |
EPA, timer 4 |
|
|
P7.7 |
EPA7/T4RST |
I/O |
EPA, timer 4 |
7-3
8XC196EA USER’S MANUAL
Table 7-2. Microcontroller Port Signals (Continued)
|
|
Special-function |
Special-function |
|
Special-function |
Port |
I/O Signal |
|
Signal Peripheral or |
||
Signal |
Signal Type |
|
|||
|
|
|
System Function |
||
|
|
|
|
|
|
|
|
|
|
|
|
Port 8 |
P8.0 |
EPA8 |
I/O |
|
EPA |
|
P8.1 |
EPA9 |
I/O |
|
EPA |
|
P8.2 |
EPA10 |
I/O |
|
EPA |
|
P8.3 |
EPA11 |
I/O |
|
EPA |
|
P8.4 |
EPA12 |
I/O |
|
EPA |
|
P8.5 |
EPA13 |
I/O |
|
EPA |
|
P8.6 |
EPA14 |
I/O |
|
EPA |
|
P8.7 |
EPA15 |
I/O |
|
EPA |
Port 9 |
P9.0 |
OS0 |
O |
|
EPA |
|
P9.1 |
OS1 |
O |
|
EPA |
|
P9.2 |
OS2 |
O |
|
EPA |
|
P9.3 |
OS3 |
O |
|
EPA |
|
P9.4 |
OS4 |
O |
|
EPA |
|
P9.5 |
OS5 |
O |
|
EPA |
|
P9.6 |
OS6 |
O |
|
EPA |
|
P9.7 |
OS7 |
O |
|
EPA |
Port 10 |
P10.0 |
SC0 |
I/O |
|
SSIO |
|
P10.1 |
SD0 |
I/O |
|
SSIO |
|
P10.2 |
SC1 |
I/O |
|
SSIO |
|
P10.3 |
SD1 |
I/O |
|
SSIO |
|
P10.4 |
EPA16 |
I/O |
|
EPA |
|
P10.5 |
— |
— |
— |
|
Port 11 |
P11.0 |
PWM0 |
O |
|
PWM |
|
P11.1 |
PWM1 |
O |
|
PWM |
|
P11.2 |
PWM2 |
O |
|
PWM |
|
P11.3 |
PWM3 |
O |
|
PWM |
|
P11.4 |
PWM4 |
O |
|
PWM |
|
P11.5 |
PWM5 |
O |
|
PWM |
|
P11.6 |
PWM6 |
O |
|
PWM |
|
P11.7 |
PWM7 |
O |
|
PWM |
Port 12 |
P12.0 |
— |
— |
— |
|
|
P12.1 |
— |
— |
— |
|
|
P12.2 |
— |
— |
— |
|
|
P12.3 |
— |
— |
— |
|
|
P12.4 |
— |
— |
— |
|
Table 7-3 lists the registers associated with the ports.
7-4
I/O PORTS
Table 7-3. Port Control and Status Registers
Mnemonic |
Address |
Description |
|
|
|
|
|
EP_DIR |
1FE3H |
Port Direction Register |
|
P2_DIR |
1FD2H |
Each bit controls the configuration of the corresponding pin. |
|
P5_DIR |
1FF3H |
||
Clearing a bit configures a pin as a complementary output; setting |
|||
P7_DIR |
1FCAH |
||
a bit configures a pin as a high-impedance input or an open-drain |
|||
P8_DIR |
1FCBH |
||
output. |
|||
P9_DIR |
1FC2H |
||
|
|||
P10_DIR |
1FC3H |
|
|
P11_DIR |
1FBAH |
|
|
P12_DIR |
1FEAH |
|
|
|
|
|
|
EP_MODE |
1FE1H |
Port Mode Register |
|
P2_MODE |
1FD0H |
Each bit controls the mode of the corresponding pin. Setting a bit |
|
P5_MODE |
1FF1H |
||
configures a pin as a special-function signal; clearing a bit |
|||
P7_MODE |
1FC8H |
||
configures a pin as a general-purpose I/O signal. |
|||
P8_MODE |
1FC9H |
||
|
|||
P9_MODE |
1FC0H |
|
|
P10_MODE |
1FC1H |
|
|
P11_MODE |
1FB8H |
|
|
P12_MODE |
1FE8H |
|
|
|
|
|
|
EP_PIN |
1FE7H |
Port Pin Register |
|
P2_PIN |
1FD6H |
Each bit reflects the current state of the corresponding pin, |
|
P3_PIN |
1FFEH |
||
regardless of the pin’s mode and configuration. |
|||
P4_PIN |
1FFFH |
||
|
|||
P5_PIN |
1FF7H |
|
|
P7_PIN |
1FCEH |
|
|
P8_PIN |
1FCFH |
|
|
P9_PIN |
1FC6H |
|
|
P10_PIN |
1FC7H |
|
|
P11_PIN |
1FBEH |
|
|
P12_PIN |
1FEEH |
|
|
|
|
|
|
P34_DRV |
1FF4H |
Ports 3/4 Driver Enable Register |
|
|
|
Bits 7 and 6 of the P34_DRV register control whether ports 3 and |
|
|
|
4, respectively, are configured as complementary or open-drain. |
|
|
|
Setting a bit configures a port as complementary; clearing a bit |
|
|
|
configures a port as open-drain. |
|
|
|
|
7-5
8XC196EA USER’S MANUAL
Table 7-3. Port Control and Status Registers (Continued)
Mnemonic |
Address |
Description |
|
|
|
|
|
EP_REG |
1FE5H |
Port Data Output Register |
|
P2_REG |
1FD4H |
For I/O Mode (Px_MODE.x = 0) |
|
P5_REG |
1FF5H |
||
When a port pin is configured as a complementary output |
|||
P7_REG |
1FCCH |
||
(Px_DIR.x = 0), setting the corresponding port data bit drives a |
|||
P8_REG |
1FCDH |
||
one on the pin, and clearing the corresponding port data bit |
|||
P9_REG |
1FC4H |
||
drives a zero on the pin. |
|||
P10_REG |
1FC5H |
||
|
|||
P11_REG |
1FBCH |
When a port pin is configured as a high-impedance input or an |
|
P12_REG |
1FECH |
open-drain output (Px_DIR.x = 1), clearing the corresponding |
|
|
|
port data bit drives a zero on the pin, and setting the corre- |
|
|
|
sponding port data bit floats the pin, making it available as a |
|
|
|
high-impedance input. |
|
|
|
For Special-function Mode (Px_MODE.x = 1) |
|
|
|
When a port pin is configured as an output (either comple- |
|
|
|
mentary or open-drain), the corresponding port data bit value is |
|
|
|
immaterial because the corresponding on-chip peripheral or |
|
|
|
system function controls the pin. |
|
|
|
To configure a pin as a high-impedance input, set both the |
|
|
|
Px_DIR and Px_REG bits. |
|
|
|
|
|
P3_REG |
1FFCH |
Port x Data Output Register |
|
P4_REG |
1FFDH |
When the port 3 or 4 pins are configured as complementary |
|
|
|
||
|
|
signals, setting a Px_REG bit drives a one on the corresponding |
|
|
|
pin and clearing a Px_REG bit drives a zero on the corresponding |
|
|
|
pin. |
|
|
|
When the port 3 or 4 pins are configured as open-drain signals, |
|
|
|
setting a Px_REG bit floats the corresponding pin and clearing a |
|
|
|
Px_REG bit drives a zero on the corresponding pin. |
|
|
|
|
The remainder of this chapter explains how to configure the ports, discusses using the port spe- cial-function signals, and describes the internal port structures.
7-6