- •CONTENTS
- •FIGURES
- •TABLES
- •1.1 Manual Contents
- •1.2 Notational Conventions and Terminology
- •1.3 Related Documents
- •1.4 Application Support Services
- •2.1 Typical Applications
- •2.2 Microcontroller Features
- •2.3 Functional Overview
- •2.3.1 Core
- •2.3.1.3 Register File
- •2.3.2 Memory Controller
- •2.4 Internal Timing
- •2.4.1 Clock and Power Management Logic
- •2.4.2 Internal Timing
- •2.4.2.1 Clock Failure Detection Logic
- •2.4.2.2 External Timing
- •2.4.2.3 Power Management Options
- •2.4.3 Internal Memory
- •2.4.4 Serial Debug Unit
- •2.4.5 Interrupt Service
- •2.5 Internal Peripherals
- •2.5.1 I/O Ports
- •2.5.2 Serial I/O (SIO) Port
- •2.5.3 Synchronous Serial I/O (SSIO) Port
- •2.5.4 Event Processor Array (EPA) and Timer/Counters
- •2.5.7 Stack Overflow Module
- •2.5.8 Watchdog Timer
- •2.6 Special Operating Modes
- •2.7 Chip Configuration Registers
- •3.1 Overview of the Instruction Set
- •3.1.1 BIT Operands
- •3.1.2 BYTE Operands
- •3.1.4 WORD Operands
- •3.1.5 INTEGER Operands
- •3.1.9 Converting Operands
- •3.1.10 Conditional Jumps
- •3.1.11 Floating-Point Operations
- •3.1.12 Extended Instructions
- •3.2 Addressing Modes
- •3.2.1 Direct Addressing
- •3.2.2 Immediate Addressing
- •3.2.3 Indirect Addressing
- •3.2.3.1 Extended Indirect Addressing
- •3.2.3.2 Indirect Addressing with Autoincrement
- •3.2.3.3 Extended Indirect Addressing with Autoincrement
- •3.2.3.4 Indirect Addressing with the Stack Pointer
- •3.2.4 Indexed Addressing
- •3.2.4.3 Extended Indexed Addressing
- •3.2.4.4 Zero-indexed Addressing
- •3.3 Considerations for Crossing Page Boundaries
- •3.4 Software Protection Features and Guidelines
- •4.1 Memory Map Overview
- •4.2 Memory Partitions
- •4.2.1 External Memory
- •4.2.2 Internal ROM
- •4.2.2.1 Program Memory in Page FFH
- •4.2.2.3 Reserved Memory Locations
- •4.2.2.4 Interrupt, PIH, and PTS Vectors
- •4.2.2.5 Chip Configuration Bytes
- •4.2.3 Internal RAM (Code RAM)
- •4.2.4.2 Peripheral SFRs
- •4.2.5 Register File
- •4.2.5.2 Stack Pointer (SP)
- •4.3 Windowing
- •4.3.1 Selecting a Window
- •4.3.2 Addressing a Location Through a Window
- •4.3.2.4 Unsupported Locations Windowing Example
- •4.3.2.5 Using the Linker Locator to Set Up a Window
- •4.3.3 Windowing and Addressing Modes
- •4.4 Controlling Read Access to the Internal ROM
- •4.5 Remapping Internal ROM
- •5.1 Functional Overview
- •5.2 Stack Operations
- •5.3 Stack Overflow Module Registers
- •5.4 Programming the Stack Overflow Module
- •5.4.1 Initializing the Stack Pointer
- •5.4.2 Enabling the Stack Overflow Module and Specifying Stack Boundaries
- •6.1 Overview of the Interrupt Control Circuitry
- •6.2 Interrupt Signals and Registers
- •6.3 Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1 PIH Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1.1 Using Software to Provide the Vector Address
- •6.3.1.2 Providing the Vector Address in Response to a CPU Request
- •6.3.2 Special Interrupts
- •6.3.2.1 Unimplemented Opcode
- •6.3.2.2 Software Trap
- •6.3.2.4 Stack Overflow
- •6.3.3 External Interrupt Signal
- •6.3.4 Shared Interrupt Requests
- •6.4 Interrupt Latency
- •6.4.1 Situations that Increase Interrupt Latency
- •6.4.2 Calculating Latency
- •6.4.2.2 PTS Interrupt Latency
- •6.5 Programming the Interrupts
- •6.5.1 Modifying Interrupt Priorities
- •6.5.2 Determining the Source of an Interrupt
- •6.6 Initializing the PTS Control Blocks
- •6.6.1 Specifying the PTS Count
- •6.6.2 Selecting the PTS Mode
- •6.6.3 Single Transfer Mode
- •6.6.4 Block Transfer Mode
- •6.6.5 Dummy Mode
- •7.1 I/O Ports Overview
- •7.2 Configuring the Port Pins
- •7.2.2 Configuring Ports 3 and 4 (Address/Data Bus)
- •7.2.3 Port Configuration Example
- •7.3.1 Address and Data Signals (Ports 3, 4, and EPORT)
- •7.3.1.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
- •7.3.5 External Interrupt Signal (Port 2)
- •7.3.6 PWM Signals (Port 11)
- •7.3.7 Serial I/O Port Signals (Ports 2 and 7)
- •7.3.8 Special Operating Mode Signal (Port 5 Pin 7)
- •7.3.9 Synchronous Serial I/O Port Signals (Port 10)
- •7.4 I/O Port Internal Structures
- •7.4.3 Internal Structure for Ports 3 and 4 (Address/Data Bus)
- •8.1 Serial I/O (SIO) Port Functional Overview
- •8.2 Serial I/O Port Signals and Registers
- •8.3 Serial Port Modes
- •8.3.1 Synchronous Mode (Mode 0)
- •8.3.2 Asynchronous Modes (Modes 1, 2, and 3)
- •8.3.2.1 Mode 1
- •8.3.2.2 Mode 2
- •8.3.2.3 Mode 3
- •8.3.2.4 Multiprocessor Communications
- •8.4 Programming the Serial Port
- •8.4.1 Configuring the Serial Port Pins
- •8.4.2 Programming the Control Register
- •8.4.3 Programming the Baud Rate and Clock Source
- •8.4.4 Enabling the Serial Port Interrupts
- •8.4.5 Determining Serial Port Status
- •CHAPTER 9 Synchronous Serial I/O (SSIO) Port
- •9.1 SSIO Port Overview
- •9.1.1 Standard Mode
- •9.1.2 Duplex Mode
- •9.2 SSIO pORT sIGNALS AND rEGISTERS
- •9.3 ssio Port Operation
- •9.3.1 Transmitting and Receiving Data
- •9.3.1.1 Normal Transfers (All Modes)
- •9.3.1.2 Handshaking Transfers (Standard Mode Only)
- •9.4 Programming the SSIO Port
- •9.4.1 Configuring the SSIO Port Pins
- •9.4.2 Configuring the SSIO Registers
- •9.4.2.1 The SSIO Baud (SSIO_BAUD) Register
- •9.4.2.3 The SSIO 0 Clock (SSIO0_CLK) Register
- •9.4.2.4 The SSIO 1 Clock (SSIO1_CLK) Register
- •9.4.3 Enabling the SSIO Interrupts
- •9.5 Programming Considerations
- •9.5.2 Standard Mode Considerations
- •9.5.3 Duplex Mode Considerations
- •10.1 PWM FUNCTIONAL OVERVIEW
- •10.2 PWM Signals and Registers
- •10.3 pwm operation
- •10.4 Programming the Frequency and Period
- •10.5 Programming the Duty Cycle
- •10.5.1 Sample Calculations
- •10.5.2 Reading the Current Value of the Down-counter
- •10.5.3 Enabling the PWM Outputs
- •10.5.4 Generating Analog Outputs
- •11.1 EPA Functional Overview
- •11.2 EPA and Timer/Counter Signals and Registers
- •11.3 Timer/Counter Functional Overview
- •11.3.1 Timer Multiplexing on the Time Bus
- •11.4 EPA Channel Functional Overview
- •11.4.1 Operating in Input Capture Mode
- •11.4.2 Operating in Output Compare Mode
- •11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels
- •11.4.4 Generating a 32-bit Time Value
- •11.4.5 Controlling a Pair of Adjacent Pins
- •11.5 Programming the EPA and Timer/Counters
- •11.5.1 Configuring the EPA and Timer/Counter Signals
- •11.5.2 Programming the Timers
- •11.5.3 Programming the Capture/Compare Channels
- •11.5.4 Programming the Compare-only (Output/Simulcapture) Channels
- •11.6 Enabling the EPA Interrupts
- •11.7 Determining Event Status
- •CHAPTER 12 Analog-to-digital (A/D) Converter
- •12.1 A/D Converter Functional Overview
- •12.2 A/D Converter Signals and Registers
- •12.3 A/D Converter Operation
- •12.4 Programming the A/D Converter
- •12.4.1 Programming the A/D Test Register
- •12.4.2 Programming the A/D Result Register (for Threshold Detection Only)
- •12.4.3 Programming the A/D Time Register
- •12.4.4 Programming the A/D Command Register
- •12.4.5 Programming the A/D Scan Register
- •12.4.6 Enabling the A/D Interrupt
- •12.5 Determining A/D Status and Conversion Results
- •12.6 Design Considerations
- •12.6.1 Designing External Interface Circuitry
- •12.6.1.1 Minimizing the Effect of High Input Source Resistance
- •12.6.1.2 Suggested A/D Input Circuit
- •12.6.1.3 Analog Ground and Reference Voltages
- •12.6.2 Understanding A/D Conversion Errors
- •CHAPTER 13 Minimum Hardware Considerations
- •13.1 Minimum Connections
- •13.1.1 Unused Inputs
- •13.1.2 I/O Port Pin Connections
- •13.2 Applying and Removing Power
- •13.3 Noise Protection Tips
- •13.4 The On-chip Oscillator Circuitry
- •13.5 Using an External Clock Source
- •13.6 Resetting the Microcontroller
- •13.6.1 Generating an External Reset
- •13.6.2 Issuing the Reset (RST) Instruction
- •13.6.3 Issuing an Illegal IDLPD Key Operand
- •13.6.4 Enabling the Watchdog Timer
- •13.6.5 Detecting Clock Failure
- •13.7 Identifying the Reset Source
- •14.1 Special Operating Mode Signals and Registers
- •14.2 Reducing Power Consumption
- •14.3 Idle Mode
- •14.3.1 Enabling and Disabling Idle Mode
- •14.3.2 Entering and Exiting Idle Mode
- •14.4 Powerdown Mode
- •14.4.1 Enabling and Disabling Powerdown Mode
- •14.4.2 Entering Powerdown Mode
- •14.4.3 Exiting Powerdown Mode
- •14.4.3.1 Generating a Hardware Reset
- •14.4.3.2 Asserting the External Interrupt Signal
- •14.4.3.3 Selecting an External Capacitor
- •14.5 ONCE Mode
- •CHAPTER 15 Interfacing with External Memory
- •15.1 Internal and External Addresses
- •15.2 External Memory Interface Signals and Registers
- •15.3 The Chip-select Unit
- •15.3.1 Defining Chip-select Address Ranges
- •15.3.2 Controlling Bus Parameters
- •15.3.3 Chip-select Unit Initial Conditions
- •15.3.4 Programming the Chip-select Registers
- •15.3.5 Example of a Chip-select Setup
- •15.4 Chip Configuration Registers and Chip Configuration Bytes
- •15.5 Bus Width and Multiplexing
- •15.5.1 A 16-bit Example System
- •15.5.2 16-bit Bus Timings
- •15.5.3 8-bit Bus Timings
- •15.5.4 Comparison of Multiplexed and Demultiplexed Buses
- •15.6 Wait States (Ready Control)
- •15.7 Bus-hold Protocol
- •15.7.1 Enabling the Bus-hold Protocol
- •15.7.2 Disabling the Bus-hold Protocol
- •15.7.3 Hold Latency
- •15.7.4 Regaining Bus Control
- •15.8 Write-control Modes
- •15.9 System Bus AC Timing Specifications
- •15.9.1 Deferred Bus-cycle Mode
- •15.9.2 Explanation of AC Symbols
- •15.9.3 AC Timing Definitions
- •16.1 Serial Debug Unit (SDU) Functional Overview
- •16.2 SDU Signals and Registers
- •16.3 SDU Operation
- •16.3.1 SDU State Machine
- •16.3.2 Code RAM Access State Machine
- •16.3.3 Minimizing Latency
- •16.4 Code RAM Access
- •16.4.1 Code RAM Data Transfer
- •16.4.2 Code RAM Access Instructions
- •16.4.3 Code RAM Data Transfer Example
- •16.5 SDU Interface Connector
- •17.1 Signals and Registers
- •17.2 Memory Protection Options
- •17.3 Entering Test-ROM Routines
- •17.3.1 Power-up and Power-down Sequences
- •17.4 ROM-dump Routine and Circuit
- •17.5 Serial Port Mode Routine
- •17.5.1 Serial Port RISM
- •17.5.2 Serial Port Mode Circuit
- •17.6 SDU RISM Execution Routine
- •17.6.1 SDU RISM Data Transfer
- •17.6.1.1 SDU RISM Data Transfer Before
- •17.6.1.2 SDU RISM Data Transfer After
- •17.6.2 SDU RISM Execution Circuit
- •17.7 RISM Command Descriptions
- •17.8 Executing Programs from Register RAM
- •17.9 RISM Command Examples
- •17.9.1 Serial Port Mode RISM Read Command Example
- •17.9.2 Serial Port Mode RISM Write Command Example
- •17.9.3 SDU RISM Execution Write Command Example
- •17.9.4 SDU RISM Execution Go Command Example
- •B.1 Functional Groupings of Signals
- •B.2 Signal Descriptions
- •B.3 Default Conditions
CHAPTER 11
EVENT PROCESSOR ARRAY (EPA)
Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs, an analog-to-digital conversion, or an interrupt. In another application, the controller may monitor an input signal to determine the status of an external device. The event processor array (EPA) was designed to reduce the processor overhead associated with these types of event control. This chapter describes the EPA and its timers and explains how to configure and program them.
11.1 EPA FUNCTIONAL OVERVIEW
The EPA performs input and output functions associated with four timer/counters, timer 1 through timer 4 (Figure 11-1). In the input mode, the EPA monitors an input pin for an event: a rising edge, a falling edge, or an edge in either direction. When the event occurs, the EPA records the value of the timer/counter so that the event is tagged with a time. This is called an input capture. Input captures are buffered to allow two captures before an overrun occurs.
In the output mode, the EPA monitors a timer/counter and compares its value with a value stored in a register. When the timer/counter value matches the stored value, the EPA can trigger an event: a timer reset, an A/D conversion, or an output event (set a pin, clear a pin, toggle a pin, or take no action). This is called an output compare.
Each input capture or output compare sets an interrupt pending bit. This bit can optionally cause an interrupt. The EPA has 17 capture/compare channels (EPA16:0) and 8 specialized compareonly channels (OS7:0). These compare-only channels can capture the value of any other timer at the time of a compare event. Capturing the timer value while simultaneously triggering the compare event output is called output/simulcapture. This feature simplifies conversion between angle and time domains or between any two time bases.
11-1
8XC196EA USER’S MANUAL
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Timer/Counter Unit |
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Timer 3 |
Timer4:1 Overflow |
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Timer 4 |
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Timer 1 |
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Timer 2 |
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Output |
OS7:0 Event |
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OS7:0 |
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Simulcapture |
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Channels 0-7 |
EPA2:0 Overrun |
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Capture/Compare |
EPA16 Event |
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EPA15:0 Event |
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EPA16:0 |
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Channels 0-16 |
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EPA16:3 Overrun |
EPAx_OVR Interrupt |
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A3401-01
Figure 11-1. EPA Block Diagram
11.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS
Table 11-1 describes the EPA and timer/counter input and output signals. Each signal shares a pin with a general-purpose I/O signal, as shown in the first column. Table 11-2 briefly describes the registers for EPA capture/compare channels, EPA compare-only channels, and timer/counters.
Table 11-1. EPA and Timer/Counter Signals
Port Pin |
EPA |
EPA |
Description |
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Signals |
Signal Type |
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P7.0 |
EPA0 |
I/O |
High-speed input/output for capture/compare |
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channel 0. |
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T1CLK |
I |
External clock source for timer 1. |
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P7.1 |
EPA1 |
I/O |
High-speed input/output for capture/compare |
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channel 1. |
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T1RST |
I |
External reset source for timer 1. |
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P7.2 |
EPA2 |
I/O |
High-speed input/output for capture/compare |
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channel 2. |
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T2CLK |
I |
External clock source for timer 2. |
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P7.3 |
EPA3 |
I/O |
High-speed input/output for capture/compare |
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channel 3. |
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T2RST |
I |
External reset source for timer 2. |
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P7.4 |
EPA4 |
I/O |
High-speed input/output for capture/compare |
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channel 4. |
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T3CLK |
I |
External clock source for timer 3. |
11-2
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EVENT PROCESSOR ARRAY (EPA) |
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Table 11-1. EPA and Timer/Counter Signals (Continued) |
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Port Pin |
EPA |
EPA |
Description |
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Signals |
Signal Type |
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P7.5 |
EPA5 |
I/O |
High-speed input/output for capture/compare |
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channel 5. |
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T3RST |
I |
External reset source for timer 3. |
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P7.6 |
EPA6 |
I/O |
High-speed input/output for capture/compare |
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channel 6. |
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T4CLK |
I |
External clock source for timer 4. |
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P7.7 |
EPA7 |
I/O |
High-speed input/output for capture/compare |
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channel 7. |
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T4RST |
I |
External reset source for timer 4. |
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P8.7:0 |
EPA15:8 |
I/O |
High-speed input/output for capture/compare |
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channels 8–15. |
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P10.4 |
EPA16 |
I/O |
High-speed input/output for capture/compare |
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channel 16. |
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P9.7:0 |
OS7:0 |
O |
Outputs of compare-only (output/simulcapture) |
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channels 0–7. |
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11-3
8XC196EA USER’S MANUAL
Table 11-2. EPA Control and Status Registers
Mnemonic |
Address |
Description |
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EPA0_CON |
1F5CH |
EPAx Capture/Compare Control |
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EPA1_CON |
1F58H |
These registers control the functions of the capture/compare |
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EPA2_CON |
1F54H |
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channels. These registers must be addressed as words. |
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EPA3_CON |
1F50H |
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EPA4_CON |
1F4CH |
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EPA5_CON |
1F48H |
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EPA6_CON |
1F44H |
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EPA7_CON |
1F40H |
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EPA8_CON |
1F3CH |
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EPA9_CON |
1F38H |
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EPA10_CON |
1F34H |
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EPA11_CON |
1F30H |
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EPA12_CON |
1F2CH |
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EPA13_CON |
1F28H |
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EPA14_CON |
1F24H |
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EPA15_CON |
1F20H |
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EPA16_CON |
1F1CH |
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EPA0_TIME |
1F5EH |
EPAx Capture/Compare Time |
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EPA1_TIME |
1F5AH |
In capture mode, these registers contain the captured timer |
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EPA2_TIME |
1F56H |
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value. In compare mode, these registers contain the time at |
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EPA3_TIME |
1F52H |
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which an event is to occur. In capture mode, these registers |
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EPA4_TIME |
1F4EH |
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are buffered to allow two captures before an overrun occurs. |
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EPA5_TIME |
1F4AH |
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In compare mode, however, they are not buffered. |
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EPA6_TIME |
1F46H |
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EPA7_TIME |
1F42H |
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EPA8_TIME |
1F3EH |
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EPA9_TIME |
1F3AH |
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EPA10_TIME |
1F36H |
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EPA11_TIME |
1F32H |
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EPA12_TIME |
1F2EH |
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EPA13_TIME |
1F2AH |
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EPA14_TIME |
1F26H |
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EPA15_TIME |
1F22H |
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EPA16_TIME |
1F1EH |
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INT_MASK |
0008H |
Interrupt Mask |
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Bit 2 in this register enables and disables the shared |
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EPAx_OVR interrupt. |
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INT_PEND |
0009H |
Interrupt Pending |
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Bit 2 in this register is set to indicate that the shared |
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EPAx_OVR interrupt is pending. |
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OS0_CON |
1EFCH |
OSx Compare-only Control |
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OS1_CON |
1EF8H |
These registers control the functions of the specialized |
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OS2_CON |
1EF4H |
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compare-only (output/simulcapture) channels. They must be |
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OS3_CON |
1EF0H |
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addressed as words. |
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OS4_CON |
1EECG |
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OS5_CON |
1EE8H |
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OS6_CON |
1EE4H |
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OS7_CON |
1EE0H |
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11-4
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EVENT PROCESSOR ARRAY (EPA) |
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Table 11-2. EPA Control and Status Registers (Continued) |
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Mnemonic |
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Description |
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OS0_TIME |
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1EFEH |
OSx Compare-only Time |
OS1_TIME |
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1EFAH |
These registers contain the time at which an event is to occur. |
OS2_TIME |
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1EF6H |
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They must be addressed as words. |
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OS3_TIME |
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1EF2H |
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OS4_TIME |
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1EEEH |
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OS5_TIME |
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1EEAH |
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OS6_TIME |
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1EE6H |
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OS7_TIME |
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1EE2H |
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P7_DIR |
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1FCAH |
Port Direction Register |
P8_DIR |
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1FCBH |
Each bit controls the configuration of the corresponding pin. |
P9_DIR |
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1FC2H |
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Clearing a bit configures a pin as a complementary output; |
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P10_DIR |
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1FC3H |
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setting a bit configures a pin as a high-impedance input or an |
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open-drain output. |
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P7_MODE |
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1FC8H |
Port Mode Register |
P8_MODE |
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1FC9H |
Each bit controls the mode of the corresponding pin. Setting a |
P9_MODE |
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1FC0H |
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bit configures a pin as a special-function signal; clearing a bit |
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P10_MODE |
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1FC1H |
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configures a pin as a general-purpose I/O signal. |
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P7_PIN |
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1FCEH |
Port Pin Register |
P8_PIN |
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1FCFH |
Each bit reflects the current state of the corresponding pin, |
P9_PIN |
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1FC6H |
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regardless of the pin’s mode and configuration. |
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P10_PIN |
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1FC7H |
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P7_REG |
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1FCCH |
Port Data Output Register |
P8_REG |
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1FCDH |
For I/O Mode (Px_MODE.x = 0) |
P9_REG |
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1FC4H |
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When a port pin is configured as a complementary output |
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P10_REG |
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1FC5H |
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(Px_DIR.x = 0), setting the corresponding port data bit |
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drives a one on the pin, and clearing the corresponding |
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port data bit drives a zero on the pin. |
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When a port pin is configured as a high-impedance input |
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or an open-drain output (Px_DIR.x = 1), clearing the corre- |
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sponding port data bit drives a zero on the pin, and setting |
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the corresponding port data bit floats the pin, making it |
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available as a high-impedance input. |
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For Special-function Mode (Px_MODE.x = 1) |
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When a port pin is configured as an output (either comple- |
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mentary or open-drain), the corresponding port data bit |
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value is immaterial because the corresponding on-chip |
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peripheral or system function controls the pin. |
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To configure a pin as a high-impedance input, set both the |
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Px_DIR and Px_REG bits. |
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PIH0_INT_MASK |
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1E98H |
Peripheral Interrupt Handler (PIH) Interrupt Mask |
PIH1_INT_MASK |
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1EA8H |
The bits in these registers enable or disable each interrupt |
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that is routed through the PIH. |
PIH0_INT_PEND |
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1E9AH |
Peripheral Interrupt Handler (PIH) Interrupt Pending |
PIH1_INT_PEND |
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1EAAH |
The bits in these registers are set by hardware to indicate that |
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a PIH interrupt source is pending. |
11-5