9.4.2.3The SSIO 0 Clock (SSIO0_CLK) Register

SSIO0_CLK

Address:

1F95H

Reset State:

00H

7

0

—

—

—

—

—

—

PHAS

POLS

Bit

Bit

Function

Number

Mnemonic

7:2

—

Reserved; for compatibility with future devices, write zeros to these bits.

1

PHAS

Phase and Polarity Select

For normal transfers, these bits determine the idle state of the serial

0

POLS

clock and select the serial clock signal edge on which the SSIO samples

incoming data bits or shifts out outgoing data bits. These bits are ignored

for handshaking transfers. Use SSIO0_ CON to select the type of data

transfer (normal or handshaking) for channel 0.

For transmissions

PHAS

POLS

0

0

low idle state; shift on falling edges

0

1

high idle state; shift on rising edges

1

0

low idle state; shift on rising edges

1

1

high idle state; shift on falling edges

For receptions

PHAS

POLS

0

0

low idle state; sample on rising edges

0

1

high idle state; sample on falling edges

1

0

low idle state; sample on falling edges

1

1

high idle state; sample on rising edges

SSIO1_CLK

Address:

1F97H

Reset State:

00H

7

0

—

—

CHS

DUP

CONINT

CONPND

PHAS

POLS

Bit

Bit

Function

Number

Mnemonic

7:6

—

Reserved; for compatibility with future devices, write zeros to these bits.

5

CHS

These bits determine the SSIO operating mode.

CHS

DUP

4

DUP

standard mode

0

0

0

1

duplex mode

1

0

channel-select half-duplex mode (uses SD1 only)

1

1

channel-select full-duplex mode (uses both SD0 and SD1)

3

CONINT

Master Contention Interrupt

For channel-select master operations, the SSIO sets the master

contention interrupt pending bit (CONPND) when the CHS# pin is

externally activated. In a system with multiple masters, an external

master activates the CHS# signal to request control of the serial clock.

CONINT determines whether the SSIO sets both CONPND and the

SSIO0 interrupt pending bit or only CONPND when the CHS# pin is

externally activated.

0 = SSIO sets only CONPND

1 = SSIO sets both CONPND and the SSIO0 interrupt pending bit

This bit is valid for channel-select master operations and ignored for all

other operations.

2

CONPND

Master Contention Interrupt Pending

For channel-select master operations, the SSIO sets this bit when the

CHS# pin is externally activated. In a system with multiple masters, an

external master activates the CHS# signal to request control of the serial

clock.

This bit is valid for channel-select master operations and ignored for all

other operations.

SSIO1_CLK (Continued)

Address:

1F97H

Reset State:

00H

7

0

—

—

CHS

DUP

CONINT

CONPND

PHAS

POLS

Bit

Bit

Function

Number

Mnemonic

1

PHAS

Phase and Polarity Select

For normal transfers, these bits determine the idle state of the serial

0

POLS

clock and select the serial clock signal edge that the SSIO samples

incoming data bits or shifts out outgoing data bits.

For transmissions

PHAS

POLS

0

0

low idle state; shift on falling edges

0

1

high idle state; shift on rising edges

1

0

low idle state; shift on rising edges

1

1

high idle state; shift on falling edges

For receptions

PHAS

POLS

0

0

low idle state; sample on rising edges

0

1

high idle state; sample on falling edges

1

0

low idle state; sample on falling edges

1

1

high idle state; sample on rising edges

These bits are ignored for duplex and channel-select modes; these

modes use SC0 as the common clock signal.

These bits are ignored for handshaking transfers. Use SSIO1_ CON to

select the type of data transfer (normal or handshaking) for channel 1.