- •CONTENTS
- •FIGURES
- •TABLES
- •1.1 Manual Contents
- •1.2 Notational Conventions and Terminology
- •1.3 Related Documents
- •1.4 Application Support Services
- •2.1 Typical Applications
- •2.2 Microcontroller Features
- •2.3 Functional Overview
- •2.3.1 Core
- •2.3.1.3 Register File
- •2.3.2 Memory Controller
- •2.4 Internal Timing
- •2.4.1 Clock and Power Management Logic
- •2.4.2 Internal Timing
- •2.4.2.1 Clock Failure Detection Logic
- •2.4.2.2 External Timing
- •2.4.2.3 Power Management Options
- •2.4.3 Internal Memory
- •2.4.4 Serial Debug Unit
- •2.4.5 Interrupt Service
- •2.5 Internal Peripherals
- •2.5.1 I/O Ports
- •2.5.2 Serial I/O (SIO) Port
- •2.5.3 Synchronous Serial I/O (SSIO) Port
- •2.5.4 Event Processor Array (EPA) and Timer/Counters
- •2.5.7 Stack Overflow Module
- •2.5.8 Watchdog Timer
- •2.6 Special Operating Modes
- •2.7 Chip Configuration Registers
- •3.1 Overview of the Instruction Set
- •3.1.1 BIT Operands
- •3.1.2 BYTE Operands
- •3.1.4 WORD Operands
- •3.1.5 INTEGER Operands
- •3.1.9 Converting Operands
- •3.1.10 Conditional Jumps
- •3.1.11 Floating-Point Operations
- •3.1.12 Extended Instructions
- •3.2 Addressing Modes
- •3.2.1 Direct Addressing
- •3.2.2 Immediate Addressing
- •3.2.3 Indirect Addressing
- •3.2.3.1 Extended Indirect Addressing
- •3.2.3.2 Indirect Addressing with Autoincrement
- •3.2.3.3 Extended Indirect Addressing with Autoincrement
- •3.2.3.4 Indirect Addressing with the Stack Pointer
- •3.2.4 Indexed Addressing
- •3.2.4.3 Extended Indexed Addressing
- •3.2.4.4 Zero-indexed Addressing
- •3.3 Considerations for Crossing Page Boundaries
- •3.4 Software Protection Features and Guidelines
- •4.1 Memory Map Overview
- •4.2 Memory Partitions
- •4.2.1 External Memory
- •4.2.2 Internal ROM
- •4.2.2.1 Program Memory in Page FFH
- •4.2.2.3 Reserved Memory Locations
- •4.2.2.4 Interrupt, PIH, and PTS Vectors
- •4.2.2.5 Chip Configuration Bytes
- •4.2.3 Internal RAM (Code RAM)
- •4.2.4.2 Peripheral SFRs
- •4.2.5 Register File
- •4.2.5.2 Stack Pointer (SP)
- •4.3 Windowing
- •4.3.1 Selecting a Window
- •4.3.2 Addressing a Location Through a Window
- •4.3.2.4 Unsupported Locations Windowing Example
- •4.3.2.5 Using the Linker Locator to Set Up a Window
- •4.3.3 Windowing and Addressing Modes
- •4.4 Controlling Read Access to the Internal ROM
- •4.5 Remapping Internal ROM
- •5.1 Functional Overview
- •5.2 Stack Operations
- •5.3 Stack Overflow Module Registers
- •5.4 Programming the Stack Overflow Module
- •5.4.1 Initializing the Stack Pointer
- •5.4.2 Enabling the Stack Overflow Module and Specifying Stack Boundaries
- •6.1 Overview of the Interrupt Control Circuitry
- •6.2 Interrupt Signals and Registers
- •6.3 Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1 PIH Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1.1 Using Software to Provide the Vector Address
- •6.3.1.2 Providing the Vector Address in Response to a CPU Request
- •6.3.2 Special Interrupts
- •6.3.2.1 Unimplemented Opcode
- •6.3.2.2 Software Trap
- •6.3.2.4 Stack Overflow
- •6.3.3 External Interrupt Signal
- •6.3.4 Shared Interrupt Requests
- •6.4 Interrupt Latency
- •6.4.1 Situations that Increase Interrupt Latency
- •6.4.2 Calculating Latency
- •6.4.2.2 PTS Interrupt Latency
- •6.5 Programming the Interrupts
- •6.5.1 Modifying Interrupt Priorities
- •6.5.2 Determining the Source of an Interrupt
- •6.6 Initializing the PTS Control Blocks
- •6.6.1 Specifying the PTS Count
- •6.6.2 Selecting the PTS Mode
- •6.6.3 Single Transfer Mode
- •6.6.4 Block Transfer Mode
- •6.6.5 Dummy Mode
- •7.1 I/O Ports Overview
- •7.2 Configuring the Port Pins
- •7.2.2 Configuring Ports 3 and 4 (Address/Data Bus)
- •7.2.3 Port Configuration Example
- •7.3.1 Address and Data Signals (Ports 3, 4, and EPORT)
- •7.3.1.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
- •7.3.5 External Interrupt Signal (Port 2)
- •7.3.6 PWM Signals (Port 11)
- •7.3.7 Serial I/O Port Signals (Ports 2 and 7)
- •7.3.8 Special Operating Mode Signal (Port 5 Pin 7)
- •7.3.9 Synchronous Serial I/O Port Signals (Port 10)
- •7.4 I/O Port Internal Structures
- •7.4.3 Internal Structure for Ports 3 and 4 (Address/Data Bus)
- •8.1 Serial I/O (SIO) Port Functional Overview
- •8.2 Serial I/O Port Signals and Registers
- •8.3 Serial Port Modes
- •8.3.1 Synchronous Mode (Mode 0)
- •8.3.2 Asynchronous Modes (Modes 1, 2, and 3)
- •8.3.2.1 Mode 1
- •8.3.2.2 Mode 2
- •8.3.2.3 Mode 3
- •8.3.2.4 Multiprocessor Communications
- •8.4 Programming the Serial Port
- •8.4.1 Configuring the Serial Port Pins
- •8.4.2 Programming the Control Register
- •8.4.3 Programming the Baud Rate and Clock Source
- •8.4.4 Enabling the Serial Port Interrupts
- •8.4.5 Determining Serial Port Status
- •CHAPTER 9 Synchronous Serial I/O (SSIO) Port
- •9.1 SSIO Port Overview
- •9.1.1 Standard Mode
- •9.1.2 Duplex Mode
- •9.2 SSIO pORT sIGNALS AND rEGISTERS
- •9.3 ssio Port Operation
- •9.3.1 Transmitting and Receiving Data
- •9.3.1.1 Normal Transfers (All Modes)
- •9.3.1.2 Handshaking Transfers (Standard Mode Only)
- •9.4 Programming the SSIO Port
- •9.4.1 Configuring the SSIO Port Pins
- •9.4.2 Configuring the SSIO Registers
- •9.4.2.1 The SSIO Baud (SSIO_BAUD) Register
- •9.4.2.3 The SSIO 0 Clock (SSIO0_CLK) Register
- •9.4.2.4 The SSIO 1 Clock (SSIO1_CLK) Register
- •9.4.3 Enabling the SSIO Interrupts
- •9.5 Programming Considerations
- •9.5.2 Standard Mode Considerations
- •9.5.3 Duplex Mode Considerations
- •10.1 PWM FUNCTIONAL OVERVIEW
- •10.2 PWM Signals and Registers
- •10.3 pwm operation
- •10.4 Programming the Frequency and Period
- •10.5 Programming the Duty Cycle
- •10.5.1 Sample Calculations
- •10.5.2 Reading the Current Value of the Down-counter
- •10.5.3 Enabling the PWM Outputs
- •10.5.4 Generating Analog Outputs
- •11.1 EPA Functional Overview
- •11.2 EPA and Timer/Counter Signals and Registers
- •11.3 Timer/Counter Functional Overview
- •11.3.1 Timer Multiplexing on the Time Bus
- •11.4 EPA Channel Functional Overview
- •11.4.1 Operating in Input Capture Mode
- •11.4.2 Operating in Output Compare Mode
- •11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels
- •11.4.4 Generating a 32-bit Time Value
- •11.4.5 Controlling a Pair of Adjacent Pins
- •11.5 Programming the EPA and Timer/Counters
- •11.5.1 Configuring the EPA and Timer/Counter Signals
- •11.5.2 Programming the Timers
- •11.5.3 Programming the Capture/Compare Channels
- •11.5.4 Programming the Compare-only (Output/Simulcapture) Channels
- •11.6 Enabling the EPA Interrupts
- •11.7 Determining Event Status
- •CHAPTER 12 Analog-to-digital (A/D) Converter
- •12.1 A/D Converter Functional Overview
- •12.2 A/D Converter Signals and Registers
- •12.3 A/D Converter Operation
- •12.4 Programming the A/D Converter
- •12.4.1 Programming the A/D Test Register
- •12.4.2 Programming the A/D Result Register (for Threshold Detection Only)
- •12.4.3 Programming the A/D Time Register
- •12.4.4 Programming the A/D Command Register
- •12.4.5 Programming the A/D Scan Register
- •12.4.6 Enabling the A/D Interrupt
- •12.5 Determining A/D Status and Conversion Results
- •12.6 Design Considerations
- •12.6.1 Designing External Interface Circuitry
- •12.6.1.1 Minimizing the Effect of High Input Source Resistance
- •12.6.1.2 Suggested A/D Input Circuit
- •12.6.1.3 Analog Ground and Reference Voltages
- •12.6.2 Understanding A/D Conversion Errors
- •CHAPTER 13 Minimum Hardware Considerations
- •13.1 Minimum Connections
- •13.1.1 Unused Inputs
- •13.1.2 I/O Port Pin Connections
- •13.2 Applying and Removing Power
- •13.3 Noise Protection Tips
- •13.4 The On-chip Oscillator Circuitry
- •13.5 Using an External Clock Source
- •13.6 Resetting the Microcontroller
- •13.6.1 Generating an External Reset
- •13.6.2 Issuing the Reset (RST) Instruction
- •13.6.3 Issuing an Illegal IDLPD Key Operand
- •13.6.4 Enabling the Watchdog Timer
- •13.6.5 Detecting Clock Failure
- •13.7 Identifying the Reset Source
- •14.1 Special Operating Mode Signals and Registers
- •14.2 Reducing Power Consumption
- •14.3 Idle Mode
- •14.3.1 Enabling and Disabling Idle Mode
- •14.3.2 Entering and Exiting Idle Mode
- •14.4 Powerdown Mode
- •14.4.1 Enabling and Disabling Powerdown Mode
- •14.4.2 Entering Powerdown Mode
- •14.4.3 Exiting Powerdown Mode
- •14.4.3.1 Generating a Hardware Reset
- •14.4.3.2 Asserting the External Interrupt Signal
- •14.4.3.3 Selecting an External Capacitor
- •14.5 ONCE Mode
- •CHAPTER 15 Interfacing with External Memory
- •15.1 Internal and External Addresses
- •15.2 External Memory Interface Signals and Registers
- •15.3 The Chip-select Unit
- •15.3.1 Defining Chip-select Address Ranges
- •15.3.2 Controlling Bus Parameters
- •15.3.3 Chip-select Unit Initial Conditions
- •15.3.4 Programming the Chip-select Registers
- •15.3.5 Example of a Chip-select Setup
- •15.4 Chip Configuration Registers and Chip Configuration Bytes
- •15.5 Bus Width and Multiplexing
- •15.5.1 A 16-bit Example System
- •15.5.2 16-bit Bus Timings
- •15.5.3 8-bit Bus Timings
- •15.5.4 Comparison of Multiplexed and Demultiplexed Buses
- •15.6 Wait States (Ready Control)
- •15.7 Bus-hold Protocol
- •15.7.1 Enabling the Bus-hold Protocol
- •15.7.2 Disabling the Bus-hold Protocol
- •15.7.3 Hold Latency
- •15.7.4 Regaining Bus Control
- •15.8 Write-control Modes
- •15.9 System Bus AC Timing Specifications
- •15.9.1 Deferred Bus-cycle Mode
- •15.9.2 Explanation of AC Symbols
- •15.9.3 AC Timing Definitions
- •16.1 Serial Debug Unit (SDU) Functional Overview
- •16.2 SDU Signals and Registers
- •16.3 SDU Operation
- •16.3.1 SDU State Machine
- •16.3.2 Code RAM Access State Machine
- •16.3.3 Minimizing Latency
- •16.4 Code RAM Access
- •16.4.1 Code RAM Data Transfer
- •16.4.2 Code RAM Access Instructions
- •16.4.3 Code RAM Data Transfer Example
- •16.5 SDU Interface Connector
- •17.1 Signals and Registers
- •17.2 Memory Protection Options
- •17.3 Entering Test-ROM Routines
- •17.3.1 Power-up and Power-down Sequences
- •17.4 ROM-dump Routine and Circuit
- •17.5 Serial Port Mode Routine
- •17.5.1 Serial Port RISM
- •17.5.2 Serial Port Mode Circuit
- •17.6 SDU RISM Execution Routine
- •17.6.1 SDU RISM Data Transfer
- •17.6.1.1 SDU RISM Data Transfer Before
- •17.6.1.2 SDU RISM Data Transfer After
- •17.6.2 SDU RISM Execution Circuit
- •17.7 RISM Command Descriptions
- •17.8 Executing Programs from Register RAM
- •17.9 RISM Command Examples
- •17.9.1 Serial Port Mode RISM Read Command Example
- •17.9.2 Serial Port Mode RISM Write Command Example
- •17.9.3 SDU RISM Execution Write Command Example
- •17.9.4 SDU RISM Execution Go Command Example
- •B.1 Functional Groupings of Signals
- •B.2 Signal Descriptions
- •B.3 Default Conditions
APPENDIX B
SIGNAL DESCRIPTIONS
This appendix provides reference information for the pin functions of the 8XC196EA.
B.1 FUNCTIONAL GROUPINGS OF SIGNALS
Table B-1 lists the signals for the 8XC196EA, grouped by function. A diagram of each package that is currently available shows the pin location of each signal.
NOTE
The datasheets are revised more frequently than this manual. As new packages are supported, the pin-out diagrams will be added to the datasheets first. If your package type is not shown in this appendix, refer to the latest datasheet to find the pin locations.
B-1
83C196EA USER’S MANUAL
Table B-1. 8XC196EA Signals Arranged by Functions
Address & Data |
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Input/Output |
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Input/Output (Cont’d) |
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Serial Debug Unit |
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Name |
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Name |
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Name |
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Name |
A20:0 |
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P2.0 |
/ TXD0 |
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P10.3 / SD1 |
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CRBUSY# |
AD15:0 |
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P2.1 |
/ RXD0 |
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P10.4 / EPA16 |
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CRDCLK |
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P2.2 |
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P10.5 |
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CRIN |
Power & Ground |
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P2.3 |
/ TXD1 |
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P11.7:0 / PWM7:0 |
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CROUT |
Name |
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P2.4 |
/ RXD1 |
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P12.4:0 |
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ANGND |
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P2.7:5 |
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Analog Inputs |
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VCC |
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P3.7:0 |
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Bus Control & Status |
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Name |
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VSS |
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P4.7:0 |
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Name |
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ACH15:0 |
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VREF |
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P5.7:0 |
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ALE |
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EPORT.7:0 |
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BHE# / WRH# |
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Processor Control |
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P7.0 |
/ EPA0 / T1CLK |
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BREQ# |
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Name |
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P7.1 |
/ EPA1 / T1RST |
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CS2:0# |
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CLKOUT |
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P7.2 |
/ EPA2 / T2CLK |
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HLDA# |
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EA# |
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P7.3 |
/ EPA3 / T2RST |
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HOLD# |
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EXTINT |
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P7.4 |
/ EPA4 / T3CLK |
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INST |
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NMI |
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P7.5 |
/ EPA5 / T3RST |
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RD# |
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ONCE# |
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P7.6 |
/ EPA6 / T4CLK |
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READY |
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PLLEN |
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P7.7 |
/ EPA7 / T4RST |
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WR# / WRL# |
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RESET# |
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P8.7:0 / EPA15:8 |
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RPD |
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P9.7:0 / OS7:0 |
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TMODE# |
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P10.0 / SC0 |
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XTAL1 |
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P10.1 / SD0 |
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XTAL2 |
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P10.2 / SC1 / CHS# |
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B-2
SIGNAL DESCRIPTIONS
AD0 / P3.0 
1
AD1 / P3.1
2
AD2 / P3.2 
3
AD3 / P3.3
4
AD4 / P3.4 
5
AD5 / P3.5
6
AD6 / P3.6 
7
AD7 / P3.7
8
VCC 
9
VCC
10
VSS 
11
VSS
12 AD8 / P4.0
13
AD9 / P4.1 
14
AD10 / P4.2
15
AD11 / P4.3 
16
AD12 / P4.4
17
AD13 / P4.5 
18
AD14 / P4.6
19
AD15 / P4.7 
20
P5.7 / RPD
21 P5.4/BREQ#/TMODE#
22 P5.6 / READY
23 P5.1 / INST
24 P5.0 / ALE
25
P5.5 / BHE# / WRH# 
26
P5.3 / RD#
27 P5.2 / WR# / WRL#
28
VSS 
29
VCC
30 A20 / EPORT.4
31
A16 / EPORT.0 
32
A17 / EPORT.1
33
A18 / EPORT.2 
34
A19 / EPORT.3
35 EPORT.5 / CS0#
36 EPORT.6 / CS1#
37 EPORT.7 / CS2#
38 NC
39 NC
40
A15 |
A14 |
A13 |
A12 |
A11 |
A10 |
A9 |
A8 |
V |
V |
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
/ OS7 |
/ OS6 |
/ OS5 |
/ OS4 |
/ OS3 |
/ OS2 |
/ OS1 |
/ OS0 |
/ EPA0 / T1CLK |
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P9.7 |
P9.6 |
P9.5 |
P9.4 |
P9.3 |
P9.2 |
P9.1 |
P9.0 |
P7.0 |
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CC |
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SS |
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160 |
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159 |
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158 |
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157 |
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156 |
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155 |
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154 |
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153 |
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152 |
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151 |
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135 |
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AS83C196EA
View of component as mounted on PC board
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54 |
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56 |
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58 |
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NC |
NC |
NC |
NC |
EA# |
V |
PLLEN |
XTAL2 |
XTAL1 |
V |
V |
CLKOUT/P2.7 |
ONCE#/P2.6 |
P2.5 |
/RXD1P2.4 |
TXD1/P2.3 |
EXTINT/P2.2 |
RXD0/P2.1 |
TXD0/P2.0 |
V |
V |
CRBUSY# |
CROUT |
CRIN |
CRDCLK |
V |
NC |
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CC |
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SS |
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CC |
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CC |
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SS |
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CC |
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EPA1 / T1RST |
EPA2 / T2CLK |
EPA3 / T2RST |
EPA4 / T3CLK |
EPA5 / T3RST |
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EPA6 / T4CLK |
EPA7 / T4RST |
EPA15 |
EPA14 |
EPA13 |
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/ / / |
/ / |
V |
V |
/ / / |
/ / |
NC |
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P7.1 |
P7.2 |
P7.3 |
P7.4 |
P7.5 |
P7.6 |
P7.7 |
P8.7 |
P8.6 |
P8.5 |
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133 |
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132 |
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131 |
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130 |
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129 |
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128 |
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127 |
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126 |
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125 |
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124 |
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123 |
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122 |
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121 |
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68 |
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69 |
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70 |
71 |
72 |
73 |
74 |
75 |
76 |
77 |
78 |
79 |
80 |
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V |
V |
ACH15 |
ACH14 |
ACH13 |
ACH12 |
ACH11 |
ACH10 |
ACH9 |
ACH8 |
ACH7 |
ACH6 |
NC |
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SS |
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SS |
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120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P8.4 / EPA12
P8.3 / EPA11
P8.2 / EPA10
P8.1 / EPA9
P8.0 / EPA8
P10.5
P10.4 / EPA16
P10.3 / SD1
P10.2 / SC1 / CHS#
P10.1 / SD0
P10.0 / SC0
P11.4 / PWM4
P11.5 / PWM5
P11.6 / PWM6
P11.7 / PWM7
P11.3 / PWM3
P11.2 / PWM2
P11.1 / PWM1
P11.0 / PWM0
VSS
VCC
P12.4
P12.0
P12.1
P12.2
P12.3
VSS
NC
VCC
NC
RESET#
NMI
VREF
ANGND
ACH0
ACH1
ACH2
ACH3
ACH4 
ACH5
† This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable.
††This pin supplies voltage to the code RAM. Maintain at 5 volts to retain data in code RAM. NC pins must be unconnected to prevent accidental entry into a test mode.
A3151-02
Figure B-1. 83C196EA 160-pin QFP Package
B-3
83C196EA USER’S MANUAL
AD0 / P3.0 
1
AD1 / P3.1
2
AD2 / P3.2 
3
AD3 / P3.3
4
AD4 / P3.4 
5
AD5 / P3.5
6
AD6 / P3.6 
7
AD7 / P3.7
8
VCC 
9
VCC
10
VSS 
11
VSS
12 AD8 / P4.0
13
AD9 / P4.1 
14
AD10 / P4.2
15
AD11 / P4.3 
16
AD12 / P4.4
17
AD13 / P4.5 
18
AD14 / P4.6
19
AD15 / P4.7 
20
P5.7 / RPD
21 P5.4/BREQ#/TMODE#
22 P5.6 / READY
23 P5.1 / INST
24 P5.0 / ALE
25
P5.5 / BHE# / WRH# 
26
P5.3 / RD#
27 P5.2 / WR# / WRL#
28
VSS 
29
VCC
30 A20 / EPORT.4
31
A16 / EPORT.0 
32
A17 / EPORT.1
33
A18 / EPORT.2 
34
A19 / EPORT.3
35 EPORT.5 / CS0#
36 EPORT.6 / CS1#
37 EPORT.7 / CS2#
38 NC
39 NC
40
A15 |
A14 |
A13 |
A12 |
A11 |
A10 |
A9 |
A8 |
V |
V |
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
/ OS7 |
/ OS6 |
/ OS5 |
/ OS4 |
/ OS3 |
/ OS2 |
/ OS1 |
/ OS0 |
/ EPA0 / T1CLK |
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P9.7 |
P9.6 |
P9.5 |
P9.4 |
P9.3 |
P9.2 |
P9.1 |
P9.0 |
P7.0 |
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CC |
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SS |
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160 |
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159 |
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158 |
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157 |
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156 |
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155 |
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154 |
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153 |
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152 |
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151 |
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150 |
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149 |
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148 |
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147 |
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146 |
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145 |
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144 |
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143 |
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142 |
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141 |
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140 |
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139 |
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138 |
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137 |
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136 |
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135 |
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134 |
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S80C196EA
View of component as mounted on PC board
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41 |
42 |
43 |
44 |
45 |
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46 |
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47 |
48 |
49 |
50 |
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51 |
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52 |
53 |
54 |
55 |
56 |
57 |
58 |
59 |
60 |
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61 |
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62 |
63 |
64 |
65 |
66 |
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67 |
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NC |
NC |
NC |
NC |
V |
V |
PLLEN |
XTAL2 |
XTAL1 |
V |
V |
CLKOUT/P2.7 |
ONCE#/P2.6 |
P2.5 |
/RXD1P2.4 |
TXD1/P2.3 |
EXTINT/P2.2 |
RXD0/P2.1 |
TXD0/P2.0 |
V |
V |
CRBUSY# |
CROUT |
CRIN |
CRDCLK |
V |
NC |
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SS |
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CC |
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SS |
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CC |
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CC |
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SS |
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CC |
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EPA1 / T1RST |
EPA2 / T2CLK |
EPA3 / T2RST |
EPA4 / T3CLK |
EPA5 / T3RST |
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EPA6 / T4CLK |
EPA7 / T4RST |
EPA15 |
EPA14 |
EPA13 |
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/ / / |
/ / |
V |
V |
/ |
/ / / |
/ |
NC |
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P7.1 |
P7.2 |
P7.3 |
P7.4 |
P7.5 |
P7.6 |
P7.7 |
P8.7 |
P8.6 |
P8.5 |
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SS |
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CC |
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133 |
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132 |
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131 |
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130 |
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129 |
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128 |
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127 |
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126 |
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125 |
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124 |
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123 |
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122 |
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121 |
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68 |
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69 |
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70 |
71 |
72 |
73 |
74 |
75 |
76 |
77 |
78 |
79 |
80 |
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SS |
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SS |
ACH15 |
ACH14 |
ACH13 |
ACH12 |
ACH11 |
ACH10 |
ACH9 |
ACH8 |
ACH7 |
ACH6 |
NC |
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V |
V |
||||||||||||||||||||||||||
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P8.4 / EPA12
P8.3 / EPA11
P8.2 / EPA10
P8.1 / EPA9
P8.0 / EPA8
P10.5
P10.4 / EPA16
P10.3 / SD1
P10.2 / SC1 / CHS#
P10.1 / SD0
P10.0 / SC0
P11.4 / PWM4
P11.5 / PWM5
P11.6 / PWM6
P11.7 / PWM7
P11.3 / PWM3
P11.2 / PWM2
P11.1 / PWM1
P11.0 / PWM0
VSS
VCC
P12.4
P12.0
P12.1
P12.2
P12.3
VSS
NC
VCC
NC
RESET#
NMI
VREF
ANGND
ACH0
ACH1
ACH2
ACH3
ACH4 
ACH5
† This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable.
††This pin supplies voltage to the code RAM. Maintain at 5 volts to retain data in code RAM. NC pins must be unconnected to prevent accidental entry into a test mode.
A6258-01
Figure B-2. 80C196EA 160-pin QFP Package
B-4