ARCHITECTURAL OVERVIEW

Table 2-5. Controlling the CLKOUT Output Frequency

2.4.2.3Power Management Options

The power saving modes selectively disable internal clocks to conserve power when the microcontroller is inactive. This microcontroller has two power-saving modes: idle and powerdown. If the power-saving modes are enabled in CCB0, the microcontroller enters a power-saving mode after executing the IDLPD instruction with a valid key (an invalid key causes a device reset). Figure 2-5 on page 2-9 illustrates the clock circuitry of the 8XC196EA.

In idle mode, the CPU stops executing instructions, but the peripheral clocks remain active. Power consumption drops to about 60% of normal execution mode consumption. Either a hardware reset or any enabled interrupt source will bring the microcontroller out of idle mode.

In powerdown mode, all internal clocks are frozen at logic state zero and the internal oscillator is shut off. The register file, internal code and data RAM, and most peripherals retain their data if VCC is maintained. Power consumption drops into the µW range.

2.4.3Internal Memory

In addition to its 1 Kbyte of register RAM, the 83C196EA has 8 Kbytes of ROM and 3 Kbytes of code/data RAM. Chapter 4, “Memory Partitions,” describes the memory contents and locations.

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8XC196EA USER’S MANUAL

2.4.4Serial Debug Unit

The serial debug unit allows you to read and write the contents of the code RAM using a highspeed, dedicated serial link. This debugging capability is new to the MCS 96 microcontroller family. The serial debug unit has four main features:

•It provides a real-time method for developing and debugging code with no CPU overhead.

•It provides a simple interface to the microcontroller without extensive external hardware.

•It supports reading and writing of all internal and external memory in interrogation mode.

•It supports breakpoints in both internal and external memory development systems.

Chapter 16, “Serial Debug Unit,” explains how to transfer data to and from the code RAM and provides examples using the SDU command instruction set.

2.4.5Interrupt Service

The microcontroller’s flexible interrupt-handling system has two main components: the programmable interrupt controller and the peripheral transaction server (PTS). The programmable interrupt controller has a hardware priority scheme that can be modified by your software. Interrupts that go through the interrupt controller are serviced by interrupt service routines that you provide. The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides high-speed, low-overhead interrupt handling. You can configure most interrupts (except NMI, stack overflow, trap, and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.

The PTS provides four special microcoded routines that enable it to complete specific tasks in much less time than an equivalent interrupt service routine can. It can transfer bytes or words, either individually or in blocks, between any memory locations in page 00H; abort PTS service if a dummy PTS request occurs; and test for a missing event in a series of regular events. PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines.

To provide additional support for the event processor array (EPA), which can generate several interrupt requests, the 8XC196EA incorporates two peripheral interrupt handlers (PIHs). A PIH provides the interrupt vector for the specific interrupt request to the interrupt controller or the PTS. See Chapter 6, “Standard and PTS Interrupts,” for more information on interrupt service options.

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