8XC196EA USER’S MANUAL
Table 17-1. Signal Descriptions (Continued)
Port |
Special-function |
Typ |
Mode |
Description |
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Pin |
Signal |
e |
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P1.2:1, |
PBUS |
I/O |
ROM-dump |
Address/Command/Data Bus |
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P4.5:0, |
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During ROM-dump, these pins serve as a regular |
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P3.7:0 |
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system bus to access external memory. Leave P4.7:6 |
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unconnected and connect P1.2:1 to serve as the |
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upper address signals. |
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P5.4 |
TMODE# |
I |
All |
Test-mode Entry Pins |
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P5.3 |
RD# |
I/O |
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To enter serial port mode, ROM-dump, or SDU RISM |
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P5.0 |
ALE |
I/O |
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execution routine, you must hold four pins low during |
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PLLEN |
— |
I |
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reset: P5.4, P5.3, P5.0, and PLLEN† . |
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P2.0 |
TXD0 |
O |
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The remaining test-mode entry pins (P2.0, P2.6, and |
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P2.6 |
HLDA#/ONCE# |
I |
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P5.2) must be high during reset. Because these pins |
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P5.2 |
WR#/WRL# |
I/O |
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have weak pull-ups internally, they will be in the |
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correct state during reset. You need only ensure that |
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your system does not drive these pins low. |
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† PLLEN=0 disables the clock doubler, so the |
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maximum frequency in test-ROM mode is FXTAL1. |
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Table 17-2. Control and Status Register |
Mnemonic |
Description |
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CCR0 |
Chip Configuration 0 Register |
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The chip configuration 0 (CCR0) register controls ROM access, enables or disables |
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idle and powerdown modes, and selects the write-control mode. It also contains the |
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bus-control parameters for fetching chip configuration byte 1. |
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17.2 MEMORY PROTECTION OPTIONS
The lock bit in chip configuration register 0 (CCR0) controls access to the ROM. Clearing CCB0.7 enables read protection. With read protection enabled, the bus controller will not read from protected areas of ROM. An attempt to read the ROM when the slave program counter contains an external address always returns F0FDH. Because the slave program counter can be as much as eight bytes ahead of the CPU program counter, the bus controller might prevent code execution from the last eight bytes of internal memory. The interrupt vectors and CCBs are not read protected because interrupts can occur even when executing from external memory. Figure 17-1 describes CCB0.
17-2
USING THE TEST-ROM ROUTINES
CCR0 |
no direct access† |
The chip configuration 0 (CCR0) register controls ROM access, enables or disables idle and powerdown modes, and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.
7 |
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0 |
LOC |
1 |
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WS1 |
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WS0 |
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DEMUX |
BHE# |
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BW16 |
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PD |
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Bit |
Bit |
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Function |
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Number |
Mnemonic |
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7 |
LOC |
Lock Bit |
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This bit controls read access to the ROM during normal operation. |
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0 |
= read protect |
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1 |
= no protection |
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Refer to “Controlling Read Access to the Internal ROM” on page 4-26 for |
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details. |
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6 |
1 |
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To guarantee proper operation, write one to this bit. |
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5:4 |
WS1:0 |
Wait States |
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These bits, along with the READY pin, control the number of wait states |
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that are used for an external fetch of chip configuration byte 1 (CCB1). |
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WS1 WS0 |
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0 |
0 |
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zero wait states |
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0 |
1 |
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one wait state |
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1 |
0 |
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two wait states |
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1 |
1 |
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three wait states |
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If READY is low when this number is reached, additional wait states are |
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added until READY is pulled high. |
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3 |
DEMUX |
Select Demultiplexed Bus |
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Selects the demultiplexed bus mode for an external fetch of CCB1: |
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0 |
= multiplexed — address and data are multiplexed on AD15:0. |
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1 |
= demultiplexed — data only on AD15:0. |
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2 |
BHE# |
Write-control Mode |
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Selects the write-control mode, which determines the functions of the |
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BHE#/WRH# and WR#/WRL# pins for external bus cycles: |
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0 |
= write strobe mode: the BHE#/WRH# pin operates as WRH#, and the |
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WR#/WRL# pin operates as WRL#. |
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1 |
= standard write-control mode: the BHE#/WRH# pin operates as |
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BHE#, and the WR#/WRL# pin operates as WR#. |
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1 |
BW16 |
Buswidth Control |
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Selects the bus width for an external fetch of CCB1: |
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0 |
= 8-bit bus |
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1 |
= 16-bit bus |
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†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1
Figure 17-1. Chip Configuration 0 (CCR0) Register
17-3
8XC196EA USER’S MANUAL
CCR0 (Continued) no direct access†
The chip configuration 0 (CCR0) register controls ROM access, enables or disables idle and powerdown modes, and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.
7 |
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0 |
LOC |
1 |
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WS1 |
WS0 |
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DEMUX |
BHE# |
BW16 |
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PD |
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Bit |
Bit |
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Function |
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Number |
Mnemonic |
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0 |
PD |
Powerdown Enable |
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Enables or disables the IDLPD #1 and IDLPD #2 instructions. When |
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enabled, the IDLPD #1 instruction causes the microcontroller to enter idle |
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mode and the IDLPD #2 instruction causes the microcontroller to enter |
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powerdown mode.0 = disable idle and powerdownmodes |
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1 = enable idle and powerdown modes |
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If your design uses idle or powerdown mode, set this bit when you |
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program the CCBs. If it does not, clearing this bit when you program the |
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CCBs will prevent accidental entry into idle or powerdown mode. |
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(Chapter 14, “Special Operating Modes,” discusses idle and powerdown |
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modes.) |
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† The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1
Figure 17-1. Chip Configuration 0 (CCR0) Register (Continued)
NOTE
The developers have made a substantial effort to provide an adequate program protection scheme. However, Intel cannot and does not guarantee that these protection methods will always prevent unauthorized access.
17-4