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- •Features
- •Pin Configuration
- •Overview
- •ATtiny11 Block Diagram
- •ATtiny12 Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •XTAL1
- •XTAL2
- •RESET
- •Status Register
- •Internal RC Oscillator
- •Crystal Oscillator
- •External Clock
- •External RC Oscillator
- •Register Description
- •Memories
- •I/O Memory
- •Register Indirect
- •I/O Direct
- •Flash Program Memory
- •EEPROM Data Memory
- •Register Description
- •Sleep Modes
- •Sleep Modes for the ATtiny11
- •Idle Mode
- •Power-down Mode
- •Sleep Modes for the ATtiny12
- •Idle Mode
- •Power-down Mode
- •Reset Sources
- •External Reset
- •Watchdog Reset
- •Register Description
- •Interrupts
- •Reset and Interrupt
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Register Description
- •I/O Port B
- •Register Description
- •Port B as General Digital I/O
- •Alternate Functions of Port B
- •Timer/Counter0
- •Timer/Counter Prescaler
- •Register Description
- •Watchdog Timer
- •Register Description
- •Analog Comparator
- •Register Description
- •Fuse Bits in ATtiny11
- •Fuse Bits in ATtiny12
- •Signature Bytes
- •ATtiny11
- •ATtiny12
- •ATtiny11/12
- •High-voltage Serial Programming
- •Low-voltage Serial Downloading (ATtiny12 only)
- •Data Polling
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •External Clock Drive ATtiny11
- •External Clock Drive ATtiny12
- •Register Summary ATtiny11
- •Register Summary ATtiny12
- •Instruction Set Summary
- •Ordering Information
- •ATtiny11
- •ATtiny12
- •Packaging Information
- •Table of Contents
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Sleep Modes
Sleep Modes for the ATtiny11
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. On wake-up from Power Down Mode on pin change, two instruction cycles are executed before the pin change interrupt flag is updated. During these cycles, the prosessor executes intructions, but the interrupt condition is not readable, and the interrupt routine has not startet yet. The contents of the register file and I/O memory are unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.
Idle Mode |
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle |
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Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys- |
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tem to continue operating. This enables the MCU to wake up from external triggered |
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interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If |
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wake-up from the Analog Comparator interrupt is not required, the analog comparator |
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can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta- |
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tus register – ACSR. This will reduce power consumption in Idle Mode. When the MCU |
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wakes up from Idle mode, the CPU starts program execution immediately. |
Power-down Mode
Sleep Modes for the ATtiny12
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Powerdown Mode. In this mode, the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog reset (if enabled), an external level interrupt (INT0), or an pin change interrupt can wake up the MCU.
Note that if a level-triggered or pin change interrupt is used for wake-up from powerdown, the changed level must be held for a time longer than the reset delay period of tTOUT. Otherwise, the MCU will fail to wake up.
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.
Idle Mode |
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle |
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Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys- |
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tem to continue operating. This enables the MCU to wake up from external triggered |
|
interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If |
|
wake-up from the Analog Comparator interrupt is not required, the analog comparator |
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can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta- |
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tus Register – ACSR. This will reduce power consumption in Idle Mode. |
Power-down Mode |
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power- |
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down Mode. In this mode, the external oscillator is stopped, while the external interrupts |
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and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog |
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ATtiny11/12
reset (if enabled), an external level interrupt (INT0), or a pin change interrupt can wake up the MCU.
Note that if a level triggered or pin change interrupt is used for wake-up from Powerdown Mode, the changed level must be held for a time to wake up the MCU. This makes the MCU less sensitive to noise. The wake-up period is equal to the clock-counting part of the reset period (See Table 10). The MCU will wake up from the power-down if the input has the required level for two watchdog oscillator cycles. If the wake-up period is shorter than two watchdog oscillator cycles, the MCU will wake up if the input has the required level for the duration of the wake-up period. If the wake-up condition disappears before the wake-up period has expired, the MCU will wake up from power-down without executing the corresponding interrupt. The period of the watchdog oscillator is 2.7 µs (nominal) at 3.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 62.
When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the reset time-out period.
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