- •Features
- •Pin Configuration
- •Overview
- •ATtiny11 Block Diagram
- •ATtiny12 Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •XTAL1
- •XTAL2
- •RESET
- •Status Register
- •Internal RC Oscillator
- •Crystal Oscillator
- •External Clock
- •External RC Oscillator
- •Register Description
- •Memories
- •I/O Memory
- •Register Indirect
- •I/O Direct
- •Flash Program Memory
- •EEPROM Data Memory
- •Register Description
- •Sleep Modes
- •Sleep Modes for the ATtiny11
- •Idle Mode
- •Power-down Mode
- •Sleep Modes for the ATtiny12
- •Idle Mode
- •Power-down Mode
- •Reset Sources
- •External Reset
- •Watchdog Reset
- •Register Description
- •Interrupts
- •Reset and Interrupt
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Register Description
- •I/O Port B
- •Register Description
- •Port B as General Digital I/O
- •Alternate Functions of Port B
- •Timer/Counter0
- •Timer/Counter Prescaler
- •Register Description
- •Watchdog Timer
- •Register Description
- •Analog Comparator
- •Register Description
- •Fuse Bits in ATtiny11
- •Fuse Bits in ATtiny12
- •Signature Bytes
- •ATtiny11
- •ATtiny12
- •ATtiny11/12
- •High-voltage Serial Programming
- •Low-voltage Serial Downloading (ATtiny12 only)
- •Data Polling
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •External Clock Drive ATtiny11
- •External Clock Drive ATtiny12
- •Register Summary ATtiny11
- •Register Summary ATtiny12
- •Instruction Set Summary
- •Ordering Information
- •ATtiny11
- •ATtiny12
- •Packaging Information
- •Table of Contents
Interrupts
Reset and Interrupt
The ATtiny11 provides four different interrupt sources and the ATtiny12 provides five. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 14. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0, etc.
Table 14. Reset and Interrupt Vectors
Vector No. |
Device |
Program Address |
Source |
Interrupt Definition |
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|
|
|
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|
|
|
External Pin, Power-on |
|
1 |
ATtiny11 |
$000 |
RESET |
Reset and Watchdog |
|
|
|
|
|
Reset |
|
|
|
|
|
|
|
|
|
|
|
External Pin, Power-on |
|
1 |
ATtiny12 |
$000 |
RESET |
Reset, Brown-out Reset |
|
|
|
|
|
and Watchdog Reset |
|
|
|
|
|
|
|
2 |
ATtiny11/12 |
$001 |
INT0 |
External Interrupt |
|
Request 0 |
|||||
|
|
|
|
||
|
|
|
|
|
|
3 |
ATtiny11/12 |
$002 |
I/O Pins |
Pin Change Interrupt |
|
|
|
|
|
|
|
4 |
ATtiny11/12 |
$003 |
TIMER0, OVF0 |
Timer/Counter0 |
|
Overflow |
|||||
|
|
|
|
||
|
|
|
|
|
|
5 |
ATtiny11 |
$004 |
ANA_COMP |
Analog Comparator |
|
|
|
|
|
|
|
5 |
ATtiny12 |
$004 |
EE_RDY |
EEPROM Ready |
|
|
|
|
|
|
|
6 |
ATtiny12 |
$005 |
ANA_COMP |
Analog Comparator |
|
|
|
|
|
|
The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny11 are:
Address |
Labels |
Code |
|
Comments |
$000 |
|
rjmp |
RESET |
; Reset handler |
$001 |
|
rjmp |
EXT_INT0 |
; IRQ0 handler |
$002 |
|
rjmp |
PIN_CHANGE |
; Pin change handler |
$003 |
|
rjmp |
TIM0_OVF |
; Timer0 overflow handler |
$004 |
|
rjmp |
ANA_COMP |
; Analog Comparator handler |
; |
|
|
|
|
$005 |
MAIN: |
<instr> |
xxx |
; Main program start |
… |
… |
… |
… |
|
The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny12 are:
Address Labels |
Code |
|
Comments |
$000 |
rjmp |
RESET |
; Reset handler |
$001 |
rjmp |
EXT_INT0 |
; IRQ0 handler |
$002 |
rjmp |
PIN_CHANGE |
; Pin change handler |
$003 |
rjmp |
TIM0_OVF |
; Timer0 overflow handler |
30 ATtiny11/12
1006F–AVR–06/07