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- •Features
- •Pin Configuration
- •Overview
- •ATtiny11 Block Diagram
- •ATtiny12 Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •XTAL1
- •XTAL2
- •RESET
- •Status Register
- •Internal RC Oscillator
- •Crystal Oscillator
- •External Clock
- •External RC Oscillator
- •Register Description
- •Memories
- •I/O Memory
- •Register Indirect
- •I/O Direct
- •Flash Program Memory
- •EEPROM Data Memory
- •Register Description
- •Sleep Modes
- •Sleep Modes for the ATtiny11
- •Idle Mode
- •Power-down Mode
- •Sleep Modes for the ATtiny12
- •Idle Mode
- •Power-down Mode
- •Reset Sources
- •External Reset
- •Watchdog Reset
- •Register Description
- •Interrupts
- •Reset and Interrupt
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Register Description
- •I/O Port B
- •Register Description
- •Port B as General Digital I/O
- •Alternate Functions of Port B
- •Timer/Counter0
- •Timer/Counter Prescaler
- •Register Description
- •Watchdog Timer
- •Register Description
- •Analog Comparator
- •Register Description
- •Fuse Bits in ATtiny11
- •Fuse Bits in ATtiny12
- •Signature Bytes
- •ATtiny11
- •ATtiny12
- •ATtiny11/12
- •High-voltage Serial Programming
- •Low-voltage Serial Downloading (ATtiny12 only)
- •Data Polling
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •External Clock Drive ATtiny11
- •External Clock Drive ATtiny12
- •Register Summary ATtiny11
- •Register Summary ATtiny12
- •Instruction Set Summary
- •Ordering Information
- •ATtiny11
- •ATtiny12
- •Packaging Information
- •Table of Contents
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ATtiny11/12 |
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External Reset |
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An external reset is generated by a low level on the |
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pin. Reset pulses longer |
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RESET |
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than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not |
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guaranteed to generate a reset. When the applied signal reaches the Reset Threshold |
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Voltage – VRST – on its positive edge, the delay timer starts the MCU after the Time-out |
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period (tTOUT) has expired. |
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Figure 19. External Reset during Operation |
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VCC |
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RESET |
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VRST |
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t TOUT |
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TIME-OUT |
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INTERNAL |
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Brown-out Detection |
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RESET |
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ATtiny12 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level |
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during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. |
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When BODEN is enabled (BODEN programmed), and VCC decreases below the trigger |
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level, the brown-out reset is immediately activated. When VCC increases above the trig- |
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ger level, the brown-out reset is deactivated after a delay. The delay is defined by the |
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user in the same way as the delay of POR signal, in Table 14. The trigger level for the |
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BOD can be selected by the fuse BODLEVEL to be 1.8V (BODLEVEL unprogrammed), |
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or 2.7V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to |
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ensure spike-free brown-out detection. |
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The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level |
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for longer than 7 µs for trigger level 2.7V, 24 µs for trigger level 1.8V (typical values). |
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Figure 20. Brown-out Reset during Operation (ATtiny12) |
VCC |
VBOT+ |
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VBOT- |
RESET |
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TIME-OUT |
tTOUT |
INTERNAL
RESET
Note: The hysteresis on VBOT: VBOT + = VBOT + 25 mV, VBOT- = VBOT - 25 mV.
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1006F–AVR–06/07