Register Description
Timer/Counter0 Control
Register – TCCR0
Timer Counter 0 – TCNT0
1006F–AVR–06/07
ATtiny11/12
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
$33 |
- |
- |
- |
- |
- |
CS02 |
CS01 |
CS00 |
TCCR0 |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R |
R |
R |
R |
R |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bits 7..3 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0
The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.
Table 18. Clock 0 Prescale Select
CS02 |
CS01 |
CS00 |
Description |
|
|
|
|
0 |
0 |
0 |
Stop, the Timer/Counter0 is stopped. |
|
|
|
|
0 |
0 |
1 |
CK |
|
|
|
|
0 |
1 |
0 |
CK/8 |
|
|
|
|
0 |
1 |
1 |
CK/64 |
|
|
|
|
1 |
0 |
0 |
CK/256 |
|
|
|
|
1 |
0 |
1 |
CK/1024 |
|
|
|
|
1 |
1 |
0 |
External Pin T0, falling edge |
|
|
|
|
1 |
1 |
1 |
External Pin T0, rising edge |
|
|
|
|
The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
$32 |
MSB |
|
|
|
|
|
|
LSB |
TCNT0 |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.
41
Timer/Counter Interrupt Mask
Register – TIMSK
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
$39 |
- |
- |
|
- |
- |
- |
- |
TOIE0 |
- |
TIMSK |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R |
R |
|
|
R |
R |
R |
R |
R/W |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
||
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
$38 |
- |
- |
- |
- |
- |
- |
TOV0 |
- |
TIFR |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R |
R |
R |
R |
R |
R |
R/W |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bits 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
42 ATtiny11/12
1006F–AVR–06/07