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Signal Processing by Digital Generalized Detector in Complex Radar Systems

43

out

n0

 

 

= xQ[k (n0 i)]xI[k (n0

i)]

 

ZDGDQI

 

 

i=1

 

 

 

n0

n0

 

 

= {cos γ[k (n0 i)]2 + ξQ[k (n0 i)]}× {sin γ[k (n0 i)]2 + ξI[k (n0 i)]}

 

i=1

i=1

 

 

n0

n0

 

 

= cos γ[k (n0 i)]2 sin γ[k (n0 i)]2 + cos γ[k (n0 i)]2 ξI[k (n0 i)]

 

 

i=1

i=1

 

 

n0

n0

 

 

+ sin γ[k (n0 i)]2 ξQ[k (n0 i)]+ ξQ[k (n0 i)]ξI[k (n0 i)];

(2.79)

 

i=1

i=1

 

out

n0

 

 

= xI[k (n0 i)]xQ[k (n0

i)]

 

ZDGDIQ

 

 

i=1

 

 

 

n0

n0

 

 

= {sin γ[k (n0 i)]2 + ξI[k (n0 i)]}× {cos γ[k (n0 i)]2 + ξQ[k (n0 i)]}

 

i=1

i=1

 

 

n0

n0

 

 

= sin γ[k (n0 i)]2 cos γ[k (n0 i)]2 + sin γ[k (n0 i)]2 ξQ[k (n0 i)]

 

 

i=1

i=1

 

 

n0

n0

 

 

+ cos γ[k (n0 i)]2 ξI[k (n0 i)]+ ξI[k (n0 i)]ξQ[k (n0 i)].

(2.80)

 

i=1

i=1

 

In the case of the phase-code-manipulated signal with duration τΣ0 = Neτ0, where Ne is the number of elementary signals and τ0 is the duration of elementary signal, the complex amplitude envelope can be presented in the following form:

 

Ne

 

 

 

(2.81)

S(t) = Si (t), where

Si (t) = exp( jθi ).

 

i =1

 

 

In the case of binary signal, we have θi = [0, π] and

 

 

 

 

= ±1.

(2.82)

 

Si (t) = ς[i]

Consequently, the discrete impulse response at the MSG output matched with the phase-code- manipulated target return signal is given by

S [i] = ς[Ne i]

(2.83)

44

Signal Processing in Radar Systems

and the in-phase and quadrature constituents of process forming at the DGD output take the following form:

 

 

 

 

Ne

Ne

 

 

ZDGDout

I

2[k] = {ς[Ne i]ς[k (Ne i)]}2 + {ξ2AFI [k (Ne i)] − ξ2PFI [k (Ne i)]}2;

 

 

 

 

 

i=1

i=1

 

 

 

 

 

(2.84)

 

 

 

 

 

 

 

 

 

 

Ne

Ne

 

ZDGDout

Q

2[k] = {ς[Ne i]ς[k (Ne i)]}2 + {ξ2AFQ [k (Ne i)] − ξ2PFQ [k (Ne i)]}2 ,

 

 

 

 

 

i=1

i=1

 

where the complex amplitude envelope of the DGD output process is defined as follows:

ZDGDout 2[k] = ZGDoutI

2[k] + ZGDoutQ

2[k].

(2.85)

Thus, in the case of the phase-code-manipulated target return signal, the DGD employed by digital signal processing subsystem in complex radar system uses only four convolving blocks. Moreover, a convolution within the limits of each cycle equal to the elementary signal duration τ0 is a summation of amplitude samples of the in-phase and quadrature constituents of the target return signal at instants with signs defined by values S*[i] = ±1 in accordance with the given code of the phasemanipulated operation. Practical realization of this principle is not difficult.

Now consider the flowchart shown in Figure 2.7 and estimate a functional ability of DGD with convolution blocks in time domain to compress the chirp-modulated target return signal. As we can see from Figure 2.7, we use eight convolving blocks. Each convolving block must carry out n0 multiplications and n0 − 1 additions of Nb numbers in the course of calculation of the k-th signal value, that is, within the limits of the sampling interval Ts. Estimate a required processing speed of the convolving block, taking into account only multiplications for the widely used case of signal processing of the chirp-modulated target return signals at the

sampling rate fs = F0 and the target return signal duration τ0 = n0Ts, namely, Vreq = n0 F0. For example, when n0 = 100 and F0 = 5 × 106 Hz, the required processing speed must be about

Vreq = 5 × 108 multiplications per second.

Consequently, in the considered case, a direct realization of convolution operations by serial digital signal processing techniques is not possible. There is a need to apply specific procedures of calculations under digital signal processing. First of all, we may use a principle of parallelism that is characteristic of convolution problems. This principle allows us to calculate n0 of pairwise multiplications S*[i] × x[k − (n0 i)], where i = 1, …, n0, simultaneously using n0 parallel multipliers with subsequent summation of partial multiplications (see Figure 2.8). In this case, each multiplier must possess the processing speed Vreq = 5 × 106 multiplications per second, that is, one multiplication operation per 40 ns. This processing speed can be easily provided by employing very large-scale integration (VLSI) circuits.

Another example of accelerated convolution operation is the implementation of a specifically designed processor that uses the read-only memory (ROM) block to store calculations of bitwise multiplications made before. Factor codes are used as result addresses of these bitwise multiplications [22,23]. Consider in detail the convolution principle carried out by a specific processor with ROM. For this case, we can present the process at the DGD output as a convolution operation in the following form to simplify calculations:

N

N

N

 

ZDGDout = 2Si Xi Xi2 + ξ2AFi ,

(2.86)

i=1

i=1

i=1

 

Signal Processing by Digital Generalized Detector in Complex Radar Systems

45

x0[k]

 

 

RAM

 

 

x[k]

x[k – 1]

x[k – 2 ] .....

x[k – (n0 1)]

 

 

 

 

 

 

 

 

RAM

 

 

 

 

 

Sn*0

 

 

 

 

 

Sn*0–1

 

 

 

 

 

Sn*0–2

 

 

 

 

.

.

 

 

 

 

.

.

 

 

 

 

.

.

 

 

 

 

.

.

 

 

 

.....

.

.

 

 

 

 

 

S1*

 

 

 

Σ

 

 

FIGURE 2.8  Principle of parallelism: RAM—the random access memory.

where

Si can be considered as the weight factors of the model signal at the MSG output Xi is the sample of the input target return signal

N is the sample size

We can assume that the input target return signals are scaled and as a sequence, |Xi| < 1. In addition, the input target return signals are presented in the form of n-bit additional comma-fixed code. Then (2.86) can be presented in the following form:

N

 

ni

 

 

ni

 

ni

 

ZDGDout = 2Si

Xi(k) 2k Xi(0)

 

Xi(k) 2k Xi(0)

 

Xi(k) 2k Xi(0)

 

i=1

 

i=1

 

 

k=1

 

i=1

 

 

ni

 

ni

 

 

+

ξ(AFk)i

2k − ξ(AF0)i

ξ(AFk)i

2k − ξ(AF0)i ,

(2.87)

 

k=1

 

k=1

 

 

where Xi(k) and ξ(i k ) are the values (0 or 1) of k-th bit of i-th sample of the input signal. The DGD output process given by (2.87) can also be presented in the following form:

n−1

 

 

ZDGDout = 2k 2

 

k=1

 

 

 

 

N

+ξ(AFk)i

i=1

N

 

N

 

 

N

 

N

Si* Xi(k) S*i

Xi(0)

Xi(k) Xi(0)

i=1

 

i=1

 

 

i=1

i=1

N

 

N

N

 

 

 

 

ξ(AF0)i

ξ(AFk)i

ξ(AF0)i

.

 

i=1

 

i=1

i=1

 

 

 

 

 

 

 

 

 

 

N

N

 

 

Xi(k) Xi(0)

 

 

i=1

i=1

 

(2.88)

(k)
N
(k)
N

46 Signal Processing in Radar Systems

Now we can introduce the function k with N binary arguments in the following form:

 

 

 

 

N

(k)

N

N

N

N

 

(k)

 

(k)

(k)

 

(k)

(k)

(k)

(k)

(2.89)

k (X1

, X2

,…, XN

) = 2Si

Xi

Xi

Xi

+ ξAFi

ξAFi .

 

 

 

 

i=1

 

 

i=1

i=1

i=1

i=1

 

In this case, (2.88) takes the following form:

 

 

 

 

 

 

 

 

 

n−1

 

 

 

 

 

 

 

 

ZDGDout

= 2k k (X1(k), X2(k),…, XN(k) )0 (X1(0), X2(0),…, XN(0) ).

(2.90)

k=1

Since arguments of the function k (X1(k) , X2(k) ,…, XN(k) ) can possess the value 0 or 1, the function k (X1(k) , X2(k) ,…, XN(k) ) is characterized by the finite number 2N of its values that can be calculated before and stored by the ROM. Now, the values of bits of the input target return signal X1(k) , X2(k) ,…, XN(k) can be used for ROM addressing to choose corresponding values of the function

k (X1(k) , X2(k) ,…, XN(k) ). Henceforth, these values will be used to determine the DGD output process ZDGDout by (2.90).

Thus, a convolution of the DGD output process ZDGDout can be obtained by n addressing to ROM, n − 1 summations, and the only subtraction (k = 0). In doing so, a number of operations occur independent of the sample size N and are determined by quantization bits of the input target return signals. A very simple block diagram of a specifically designed processor that produces a convolution in accordance with (2.90) is presented in Figure 2.9.

Pulse packet of the target return signals is shifted by turns at the shift registers SR1,…, SRN starting from the low-order bit. At first, the values Xi(n−1) at the output of each shift register are

used for addressing the corresponding value of the function (X(k) , X(k) ,…, X ) from ROM.

n 1 1 2

This value is loaded in the register R1 and added to the register R2 content (zero content at the first step). The obtained result is recorded by the register R3. At the next cycle, the value of the functionn−2 (X1(k) , X2(k) ,…, X ) is chosen and the content of the register R3 (the previous sum) is recorded by the register R2, with the right shift on one bit that corresponds to multiplication on the factor 0.5. The content of the register R1, that is, the value of the function n−2 (X1(k) , X2(k) ,…, XN(k) ), is added to

the content of the register R2 that is a value of the function 0.5 n1(X1(k), X2(k),…, XN(k) ). As a result,

SR1

 

 

SR2

 

 

 

 

.....

 

 

 

SRN

 

x(Nk)

 

 

 

 

 

 

 

 

 

 

x1(k)

 

 

 

x2(k)

 

 

x(Nk) 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R1

 

 

R2

 

 

2–1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Σ

R3

FIGURE 2.9  Processor specifically designed: SR, the shift register; and R, the register.

(k)
N

Signal Processing by Digital Generalized Detector in Complex Radar Systems

47

we obtain a regular particular result. This operation is repeated n times, and in doing so, at the last step, the function 0 (X1(0), X2(0),…, XN(0) ) is subtracted from the accumulated sum and the final result of convolution given by (2.90) is the content of the register R3 after n cycles.

As we can see, a realization of the considered accelerated convolution is not difficult for low values of the sample size N, for example, N = 10…12. With increasing N, the required ROM size becomes very large, for example, at N = 15, QROM = 32798 words, and an access time is increased essentially. We can decrease the ROM size by partitioning a calculation process using a set of steps with later summing up results. Assume N = LM, where M is the number of functions k (X1(k) , X2(k) ,…, X ) and L is the number of binary arguments of these functions, then, in this case, (2.86) can be written in the following form:

L

2L

N

ZDGDout =( 2Si Xi Xi2 + ξ2AFi )+ ( 2Si Xi Xi2 + ξ2AFi )Xi2 + +

( 2Si Xi Xi2 + ξ2AFi ).

i=1

i= L+1

i= (M −1)(L+1)

(2.91)

Each individual sum can be determined by the earlier-described procedure. For this case, the ROM size is determined as QROM = 2LM instead of 2N = 2M × 2L without the partition of calculation process.

2.4  CONVOLUTION IN FREQUENCY DOMAIN

Now, consider the features of discrete convolution in frequency domain. In accordance with the theory of discrete presentation of continuous functions limited by time or frequency, the function X(t) that can be presented by a sequence of readings {X[i]}, i = 0, 1, 2,…, n − 1 is transformed in frequency domain by discrete Fourier transform (DFT) that for each k = 0, 1, 2,…, n − 1 takes the following form [24]:

n−1

 

j2πik

n−1

 

 

 

ik

 

 

FX (k) = X[i]exp

 

 

= X[i]Wn

,

(2.92)

n

i= 0

 

 

i= 0

 

 

 

 

 

 

 

where

 

j2π

 

 

Wn = exp

 

 

,

(2.93)

n

 

 

 

 

and vice versa, any function presented by the limited discrete spectrum {FX[k]}, k = 0, 1, 2,…, n − 1, can be reconstructed in the time domain using the inverse discrete Fourier transform (IDFT):

 

1

n−1

j2πki

 

1

n−1

 

X[i] =

 

FX [k]exp

 

 

=

 

FX [k]Wnik .

(2.94)

n

n

n

 

k = 0

 

 

 

k = 0

 

 

 

 

 

 

 

 

 

Note that the number of discrete elements of the function X(t) is the same for its presentation both in the time domain and in the frequency domain.

Convolution of sequences in the frequency domain is reduced to product of DFT results. For this purpose, there is a need to realize two direct Fourier transforms, namely, to convolve a sequence of readings of the function {X[i]}, i = 0, 1, 2,…, n − 1 and a sequence of readings of the impulse response of filters used by DGD. If after convolution it is necessary to make transformations into the time domain, there is a need to carry out IDFT for sequence of spectral components {FX[k]}, k = 0, 1, 2,…, n − 1.

ZDGDout p

48

Signal Processing in Radar Systems

For complex functions (signals) an algorithm of the operation DFT-Convolution-IDFT takes the following form:

 

n−1

 

 

 

 

 

ik

, k = 0,1, 2,…, n − 1,

(2.95)

1. FH [k] = H[i]Wn

i= 0

.

where H[i] is a sequence of readings of the complex impulse response of the convolving filter:

 

l −1

 

 

 

 

 

ik

,

(2.96)

2. FX [k] = X[i]Wl

 

i= 0

.

where X[i] is a sequence of complex readings of the input (convolved) function (the target return signal).

3. F out [k] = FH [k]FX [k] , k = 0,1,…,l + n − 1.

(2.97)

ZDGD

 

l+ n−1

4. ZoutDGD[i] = l +1 n FZDGDout [k]Wl+ikn−1, i = 0,1,…,l + n − 1. (2.98)

k = 0

Principal peculiarity of the considered algorithm is a group technology type flow procedure if the width of an input data array is higher n, that is, l n. The resulting convolution width is l + n − 1. Under solution of detection problems by DGD, we assume that the impulse response of all filters used by DGD is not variable, at least for probing signals of the same kind. Therefore, the DFT of impulse response of all filters used by DGD is carried out in advance and stored in the memory device of the corresponding computer. In the course of convolution, there is a need to accomplish one DFT and one IDFT. It must be emphasized that under radar detection and signal processing problems, a convolved sequence width L corresponds to radar range sweep length that is much more in comparison with the width of convolving sequence equal to the width of an impulse response nim of filters used by DGD. In accordance with Section 2.1, nim = n0, where n0 is the number of discrete elements of the expected target return signal. Synchronous convolution of such sequences is a very cumbersome process. Because of this, as a rule, the input sequence is divided.on blocks with the width l. Each element of the p-th block is generated from a general sequence {X[i]}, i = 0, 1, 2,…, L following the law

Zp[i] = Z[i + pl],

L

 

 

n = 0,1, 2,, In

 

 

,

(2.99)

 

 

l

 

where In[L/l] is the integer part of the ratio in brackets.

For each input data block of the width l the (l + n − 1)-point DFT is determined. For convolving sequence of impulse response of filters used by DGD the components of the (l + n − 1)-point DFT must be determined in advance and stored in a memory device. Convolution in frequency domain for each block is obtained by multiplication between the DFT of convolved and convolving sequences at (l + n − 1) points. To determine the convolution in time domain the IDFT is accomplished. The widths of obtained sequence ZDGDout p [i] are equal to (l + n − 1) and the neighboring sequences

[i] and ZDGDout p+1 [i] are overlapped at the n − 1 points. Thus, only the l sequence values will be true. Furthermore, the sum of overlapping partial sequences is used to obtain the correct calculation

Signal Processing by Digital Generalized Detector in Complex Radar Systems

49

results for ZDGDout [i] in all points. In the course of design process, the problem of selecting the optimal

value l at a fixed n by criterion of minimum convolution time arises. At low values of nim 100 the condition lopt ≈ 5nim is satisfied [11,21].

Consider now the problem of work content to realize the DGD in frequency domain. DFT or IDFT requires (l + n − 1)2 operations of multiplication and (l + n − 1) operations of summation for complex values to obtain the (l + n − 1) frequency (time) samples. The total number of required operations taking into account transformations from the frequency domain to the time domain after convolution consists of 2(l + n − 1)2 + (l + n − 1) multiplications and 2(l + n − 1) summations for complex values. In doing so, we obtain the sample of the output data with the width l. To obtain the same length for output data in the time domain, l2 operations of multiplications and l − 1 operations of summations are required for complex values. Consequently, a convolution in the frequency domain is more time-consuming compared to a convolution in the time domain, approximately eight times if lopt nim. Thus, there is no purpose to implement a convolution in the discussed form for DGD.

We can essentially decrease the number of operations at convolution in the frequency domain by employing the specific DFT algorithms that are called the fast FT (FFT) [25]. Now, consider the design principles of the FFT algorithm with time decimation by modulus 2 of real sequence. Let the sequence {X[i]} that is processed by DFT have the width M corresponding to the integer power of the number 2, that is, M = 2m. This initial sequence can be divided into two parts in accordance with the following rule:

Xeven[i] = X[2i] and Xodd[i] = X[2i +1] , i = 0,1,…, 0.5M.

(2.100)

The sequence Xeven[i] consists of elements of the initial sequence with even numbers, and the sequence Xodd[i] consists of elements of the initial sequence with odd numbers. The width of each

sequence is equal to 0.5M. The sequences obtained in the issue of expansion are expanded again in two parts, while 0.5M two-point sequences are delivered. The number of expansion steps is equal

to m = log2M.

The essence of the FFT algorithm with time decimation by modulus 2 is as follows. The DFT sequences with the width l > 2 are calculated by a combination of DFT of two sequences with the width equal to 0.5 l. In accordance with this fact, at first, the 0.5M-point DFT of two sequences is carried out under processing of the M-point sequence by FFT. Then the obtained transformations are united for the purpose of creating the 0.25M four-point sequences, 0.125M eight-point sequences, and so on, while a transformation of the width M will be obtained after m steps. FFT determination is carried out by the following formulas:

F[k] = Feven[k] + Fodd[k]WMk , k = 0,1,…, 0.5M − 1,

(2.101)

F[k + 0.5M] = Feven[k] − Fodd[k]WMk , k = 0,1,…,0.5M − 1,

(2.102)

where

 

 

 

0.5M −1

 

Feven[k] =

Xeven[i]W0ik.5M

(2.103)

 

i= 0

 

and

 

 

 

0.5M −1

 

Fodd[k] =

Xodd[i]W0ik.5M

(2.104)

i= 0

50

 

 

Signal Processing in Radar Systems

X[0]

W08

 

W08

F[0]

X[4]

 

F[4]

 

 

 

X[2]

W28

 

W18

F[1]

X[6]

 

F[5]

 

 

 

X[1]

W08

W28

 

F[2]

X[5]

 

F[6]

 

 

 

X[3]

W28

W38

 

F[3]

X[7]

 

F[1]

 

 

 

Stage 1

Stage 2

 

Stage 3

 

FIGURE 2.10  The directed graph for 8-point FFT.

are DFT for even and odd sequences, correspondingly; WMk = (WM )k is the k-th power of the factor WM, which is called rotating factor.

Directed graphs are used to represent graphically the FFT algorithm. The following notations are implemented under graphical representations: The point (or circle) denotes the summation– subtraction operation, the final sum appearing at the top output branch and the final subtraction appearing at the bottom output branch; the arrow on the branch denotes the multiplication by constant written over the arrow; if the arrow is absent the constant factor is equal to unit. The directed graph for 8-point FFT with time decimation by modulus 2 is shown in Figure 2.10. An order of input data assignment is obtained using a procedure of binary inversion of the numbers 0, 1, 2, 7. Such procedure makes a representation simpler and allows us to obtain the input sequence in the natural order—F[0], F[1], F[2], F[3] at the top output branches and F[4], F[5], F[6], F[7] at the bottom output branches. As we can see from Figure 2.10, the 8-point FFT is accomplished over three steps.

At the first step, the four 2-point DFTs are implemented and the condition W2 = exp{−jπ} = −1 is taken into consideration. By this reason, the multiplication operations are absent, and in accordance with (2.98), we can write

F[0] = Feven[0] + Fodd[0] and F[1] = Feven[0] − Fodd[0].

(2.105)

At the second step, two pairs of 2-point FFTs are combined with two 4-point FFTs according to (2.101). At the third step, two 4-point FFTs are transformed into the 8-point FFT. In general, the number of steps is defined as m = log2M. At each step, excluding the first step, one half of M multiplications and M summations for complex values are processed. For this reason, to determinate M-point FFT we need (M/2)log2M multiplication operations and Mlog2M summation operations for complex values.

Previously it was shown that to determine the DFT we need M2 multiplications and M summations for the complex values. The advantage in the number of multiplication operations under realization of FFT in comparison with the direct DFT is

ν =

M2

=

2M

.

(2.106)

(M /2) log2 M

 

 

 

log2 M

 

For example, ν ≈ 200 at M = 1024, ν ≈ 21 at M = 128.

Signal Processing by Digital Generalized Detector in Complex Radar Systems

51

 

 

RAM

 

 

 

FFT

 

 

 

.....

 

 

 

input

 

 

processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

xI[k]

 

xQ[k]

 

 

 

 

 

 

 

 

 

 

.....

 

 

 

 

 

.....

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.....

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM model signal

IFFT processor

 

 

 

RAM

 

.....

 

 

 

 

 

output

 

 

 

 

 

 

 

 

 

 

 

 

ZIout[k]

 

 

ZQout[k]

 

 

FIGURE 2.11  The FFT-specific processor.

Now, return to the problem of signal processing in frequency domain for DGD taking into account the FFT implementation. A flowchart of the corresponding FFT-specific processor is shown in Figure 2.11. The FFT-specific processor consists of the input memory device, FFT processor, IFFT processor, ROM device, multiplier, and output memory device. As can be seen from Figure 2.11, the in-phase and quadrature constituents of the target return signal come in at the input memory device simultaneously. The in-phase and quadrature constituents of the target return signal form the complex signal subjected to the transformation FFT-Multiplication-IFFT. Because of this, the input and output memory devices and all intermediate registers must possess a double bit width.

For signal processing by the DGD there is a need to carry out the FFT, IFFT, and multiplication between 2 × M-point complex values. Furthermore, we assume that M = l + n − 1. Since the main operation time of the considered specific processor is spent by multiplications between complex and complex conjugate values, the number of convolution operations can be presented in the following form:

Nsp = 2[0.5M log2 M] + m = M[1 + log2 M].

(2.107)

The number of convolution operations for the in-phase and quadrature constituents of one sequence of the output signal is determined by

Nsp

 

M[l + log2

M]

 

(2.108)

l =

l

 

.

 

 

Under direct calculations in time domain, the number of multiplications between the complex values for a single sample is equal to n at l = n. Consequently, a gain in the number of multiplication operations for complex and complex conjugate values implementing the direct FFT can be determined in the following form:

gFFT =

 

n2

 

=

 

n

 

.

(2.109)

M[1

+ log2

M]

2[1

+ log2

2n]

 

 

 

 

Calculations made by this formula show that the gain gFFT > 1 can be obtained only for the case

l 12. Thus, at l = 2048 we obtain gFFT = 85. It can be seen that a greater gain in the number of multiplication operations between the complex and complex conjugate values can be obtained only

for high-width sequences.

Now, let us evaluate the required memory size to realize the DGD in radar signal processing subsystem under the implementation of the FFT. Using the same memory storage cells for FFT and IFFT and the buffer to store the output signal (see Figure 2.11), the memory size required for functional DGD purposes is Q = M1 + M2 + M3 + l, where M1 is the number of storage cells required for input sequence sells, M2 is the number of storage cells required for FFT and IFFT, M3 is the number

52

Signal Processing in Radar Systems

of storage cells required for spectral components of impulse responses of all filters used by DGD, and l is the number of storage cells required for the output sequence. Thus, the use of FFT requires higher memory size in comparison with the implementation of FT in the frequency domain. A frequency of convolution operations can be essentially increased using a continuous-flow FFT system. In this case, the specific processor for FFT consists of 0.5M log2M devices for arithmetic operations functioning in parallel. Each arithmetic device fulfills a transformation at a definite stage of FFT. In doing so, we can reduce the calculation time in log2 0.5M times. The continuous-flow FFT system requires additional memory in the form of interstage delay registers.

2.5  EXAMPLES OF SOME DGD TYPES

At the initial stage of designing, first of all, there is a need to define the following parameters of digital signal processing by DGD: the sampling rate fs and the width of digit capacity of the target return signal amplitude samples Nb. DGD performance and requirements of digital signal processing devices used by DGD depend strongly on a choice of these parameters. Corresponding practical recommendations can be delivered by analyzing different types of DGD designing and construction by computer simulation. In what follows, we present some of the DGD simulation results for chirpmodulated target return signals with the frequency deviation F0 equal to 5 MHz.

With the sampling theorem viewpoint, the sampling period Ts of chirp-modulated signals is considered like the limiting case if the following condition Tsmax = 1/ F0 is satisfied for the in-phase and quadrature channels. The curve 1 in Figure 2.12 corresponds to the DGD output signal at various values Ts in neighboring area relatively to the peak of compressed signal. At Ts = 1/ F0 the DGD output signal is represented by a single point in the main lobe area (the point a in Figure 2.12). The main lobe area width near its base is equal to 2/ F0.

In general, the DGD output signal has big side lobes with amplitudes for about one-half amplitude of the main lobe, which is undesirable. At Ts = 1/2 F0, in other words, when the sampling rate is two times higher than the limiting sampling rate fsmax, two readings are within the limits of the main peak with the width equal to 1/ F0. At Ts = 1/5 F0, the DGD output signal is close to the analog GD output signal. As evident from the simulation results discussed, the sampling rate must be at

ZDGDout (Nb)

 

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

1 Ts =

1

 

 

 

 

 

 

 

F0

 

 

 

 

 

 

 

2 Ts =

1

 

 

 

 

 

 

 

 

F0

 

 

 

 

 

 

 

3 Ts =

1

 

 

 

 

 

 

 

F0

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

2

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

t

5.2

 

 

 

 

 

F0–1 = 0.2 × 10–6

 

FIGURE 2.12  The DGD output signal amplitude versus the sampling period Ts.

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