- •PERFORMANCE FEATURES
- •FUNCTIONAL BLOCK DIAGRAM
- •INTEGRATION FEATURES
- •SYSTEM INTERFACE FEATURES
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •DSP Core Architecture
- •DSP Peripherals Architecture
- •Figure 1. System Diagram
- •Memory Architecture
- •Figure 2. Memory Map
- •Internal (On-Chip) Memory
- •External (Off-Chip) Memory
- •External Memory Space
- •I/O Memory Space
- •Boot Memory Space
- •Interrupts
- •DMA Controller
- •Host Port
- •Host Port Acknowledge (HACK) Modes
- •Host Port Chip Selects
- •DSP Serial Ports (SPORTs)
- •Serial Peripheral Interface (SPI) Ports
- •UART Port
- •Programmable Flag (PFx) Pins
- •Low Power Operation
- •Idle Mode
- •Power-Down Core Mode
- •Power-Down Core/Peripherals Mode
- •Power-Down All Mode
- •Clock Signals
- •Figure 3. External Crystal Connections
- •Reset
- •Power Supplies
- •Power-Up Sequence
- •Booting Modes
- •Bus Request and Bus Grant
- •Instruction Set Description
- •Development Tools
- •Designing an Emulator-Compatible DSP Board (Target)
- •Target Board Header
- •Figure 4. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 5. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 6. JTAG Pod Connector Dimensions
- •Figure 7. JTAG Pod Connector Keep-Out Area
- •Design-for-Emulation Circuit Information
- •Additional Information
- •PIN FUNCTION DESCRIPTIONS
- •SPECIFICATIONS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •Power Dissipation
- •TIMING SPECIFICATIONS
- •Clock In and Clock Out Cycle Timing
- •Figure 8. Clock In and Clock Out Cycle Timing
- •Programmable Flags Cycle Timing
- •Figure 9. Programmable Flags Cycle Timing
- •Timer PWM_OUT Cycle Timing
- •Figure 10. Timer PWM_OUT Cycle Timing
- •External Port Write Cycle Timing
- •Figure 11. External Port Write Cycle Timing
- •External Port Read Cycle Timing
- •Figure 12. External Port Read Cycle Timing
- •External Port Bus Request and Grant Cycle Timing
- •Figure 13. External Port Bus Request and Grant Cycle Timing
- •Host Port ALE Mode Write Cycle Timing
- •Figure 14. Host Port ALE Mode Write Cycle Timing
- •Host Port ACC Mode Write Cycle Timing
- •Figure 15. Host Port ACC Mode Write Cycle Timing
- •Host Port ALE Mode Read Cycle Timing
- •Figure 16. Host Port ALE Mode Read Cycle Timing
- •Host Port ACC Mode Read Cycle Timing
- •Figure 17. Host Port ACC Mode Read Cycle Timing
- •Serial Ports
- •Figure 18. Serial Ports
- •Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5tSCLK)
- •Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5tHCLK)
- •Serial Peripheral Interface (SPI) Port—Master Timing
- •Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
- •Serial Peripheral Interface (SPI) Port—Slave Timing
- •Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
- •Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
- •Figure 23. UART Port—Receive and Transmit Timing
- •JTAG Test And Emulation Port Timing
- •Figure 24. JTAG Port Timing
- •Output Drive Currents
- •Figure 25. Typical Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Disable Time
- •Figure 26. Output Enable/Disable
- •Figure 27. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Figure 28. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
- •Output Enable Time
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Figure 30. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)
- •Environmental Conditions
- •Thermal Characteristics
- •144-Lead LQFP Pinout
- •144-Lead Mini-BGA Pinout
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
- •Revision History
ADSP-2191M
144-Lead LQFP Pinout
Table 25 lists the LQFP pinout by signal name. Table 26 lists the LQFP pinout by pin.
Table 25. 144-Lead LQFP Pins (Alphabetically by Signal)
|
Pin |
|
Pin |
|
Pin |
|
Pin |
|
Pin |
Signal |
No. |
Signal |
No. |
Signal |
No. |
Signal |
No. |
Signal |
No. |
|
|
|
|
|
|
|
|
|
|
A0 |
84 |
BYPASS |
72 |
GND |
33 |
HCMS |
27 |
TCLK1 |
65 |
A1 |
85 |
CLKIN |
132 |
GND |
54 |
HCIOMS |
28 |
TCLK2 |
47 |
A2 |
86 |
CLKOUT |
130 |
GND |
55 |
HRD |
31 |
TDI |
75 |
A3 |
87 |
D0 |
123 |
GND |
77 |
HWR |
32 |
TDO |
74 |
A4 |
88 |
D1 |
124 |
GND |
80 |
IOMS |
114 |
TFS0 |
59 |
A5 |
89 |
D2 |
125 |
GND |
94 |
MS0 |
115 |
TFS1 |
66 |
A6 |
91 |
D3 |
126 |
GND |
105 |
MS1 |
116 |
TFS2 |
48 |
A7 |
92 |
D4 |
128 |
GND |
129 |
MS2 |
117 |
TMR0 |
43 |
A8 |
93 |
D5 |
135 |
GND |
134 |
MS3 |
119 |
TMR1 |
44 |
A9 |
95 |
D6 |
136 |
HA16 |
23 |
OPMODE |
83 |
TMR2 |
45 |
A10 |
96 |
D7 |
137 |
HACK |
26 |
PF0 |
34 |
TMS |
76 |
A11 |
97 |
D8 |
138 |
HACK_P |
24 |
PF1 |
35 |
TRST |
79 |
A12 |
98 |
D9 |
139 |
HAD0 |
3 |
PF2 |
36 |
TXD |
53 |
A13 |
99 |
D10 |
140 |
HAD1 |
4 |
PF3 |
37 |
VDDEXT |
13 |
A14 |
101 |
D11 |
141 |
HAD2 |
6 |
PF4 |
38 |
VDDEXT |
25 |
A15 |
102 |
D12 |
142 |
HAD3 |
7 |
PF5 |
39 |
VDDEXT |
40 |
A16 |
103 |
D13 |
144 |
HAD4 |
8 |
PF6 |
41 |
VDDEXT |
63 |
A17 |
104 |
D14 |
1 |
HAD5 |
9 |
PF7 |
42 |
VDDEXT |
90 |
A18 |
106 |
D15 |
2 |
HAD6 |
10 |
RCLK0 |
61 |
VDDEXT |
100 |
A19 |
107 |
DR0 |
60 |
HAD7 |
11 |
RCLK1 |
68 |
VDDEXT |
118 |
A20 |
108 |
DR1 |
67 |
HAD8 |
12 |
RCLK2 |
50 |
VDDEXT |
131 |
A21 |
109 |
DR2 |
49 |
HAD9 |
14 |
RD |
122 |
VDDEXT |
143 |
ACK |
120 |
DT0 |
56 |
HAD10 |
15 |
RESET |
73 |
VDDINT |
19 |
BG |
111 |
DT1 |
64 |
HAD11 |
17 |
RFS0 |
62 |
VDDINT |
58 |
BGH |
110 |
DT2 |
46 |
HAD12 |
18 |
RFS1 |
69 |
VDDINT |
82 |
BMODE0 |
70 |
EMU |
81 |
HAD13 |
20 |
RFS2 |
51 |
VDDINT |
127 |
BMODE1 |
71 |
GND |
5 |
HAD14 |
21 |
RXD |
52 |
WR |
121 |
BMS |
113 |
GND |
16 |
HAD15 |
22 |
TCK |
78 |
XTAL |
133 |
BR |
112 |
GND |
29 |
HALE |
30 |
TCLK0 |
57 |
|
|
|
|
|
|
|
|
|
|
|
|
REV. A |
–43– |
ADSP-2191M
Table 26. 144-Lead LQFP Pins (Numerically by Pin Number)
Pin |
|
Pin |
|
Pin |
|
Pin |
|
Pin |
|
No. |
Signal |
No. |
Signal |
No. |
Signal |
No. |
Signal |
No. |
Signal |
|
|
|
|
|
|
|
|
|
|
1 |
D14 |
30 |
HALE |
59 |
TFS0 |
88 |
A4 |
117 |
MS2 |
2 |
D15 |
31 |
HRD |
60 |
DR0 |
89 |
A5 |
118 |
VDDEXT |
3 |
HAD0 |
32 |
HWR |
61 |
RCLK0 |
90 |
VDDEXT |
119 |
MS3 |
4 |
HAD1 |
33 |
GND |
62 |
RFS0 |
91 |
A6 |
120 |
ACK |
5 |
GND |
34 |
PF0 |
63 |
VDDEXT |
92 |
A7 |
121 |
WR |
6 |
HAD2 |
35 |
PF1 |
64 |
DT1 |
93 |
A8 |
122 |
RD |
7 |
HAD3 |
36 |
PF2 |
65 |
TCLK1 |
94 |
GND |
123 |
D0 |
8 |
HAD4 |
37 |
PF3 |
66 |
TFS1 |
95 |
A9 |
124 |
D1 |
9 |
HAD5 |
38 |
PF4 |
67 |
DR1 |
96 |
A10 |
125 |
D2 |
10 |
HAD6 |
39 |
PF5 |
68 |
RCLK1 |
97 |
A11 |
126 |
D3 |
11 |
HAD7 |
40 |
VDDEXT |
69 |
RFS1 |
98 |
A12 |
127 |
VDDINT |
12 |
HAD8 |
41 |
PF6 |
70 |
BMODE0 |
99 |
A13 |
128 |
D4 |
13 |
VDDEXT |
42 |
PF7 |
71 |
BMODE1 |
100 |
VDDEXT |
129 |
GND |
14 |
HAD9 |
43 |
TMR0 |
72 |
BYPASS |
101 |
A14 |
130 |
CLKOUT |
15 |
HAD10 |
44 |
TMR1 |
73 |
RESET |
102 |
A15 |
131 |
VDDEXT |
16 |
GND |
45 |
TMR2 |
74 |
TDO |
103 |
A16 |
132 |
CLKIN |
17 |
HAD11 |
46 |
DT2 |
75 |
TDI |
104 |
A17 |
133 |
XTAL |
18 |
HAD12 |
47 |
TCLK2 |
76 |
TMS |
105 |
GND |
134 |
GND |
19 |
VDDINT |
48 |
TFS2 |
77 |
GND |
106 |
A18 |
135 |
D5 |
20 |
HAD13 |
49 |
DR2 |
78 |
TCK |
107 |
A19 |
136 |
D6 |
21 |
HAD14 |
50 |
RCLK2 |
79 |
TRST |
108 |
A20 |
137 |
D7 |
22 |
HAD15 |
51 |
RFS2 |
80 |
GND |
109 |
A21 |
138 |
D8 |
23 |
HA16 |
52 |
RXD |
81 |
EMU |
110 |
BGH |
139 |
D9 |
24 |
HACK_P |
53 |
TXD |
82 |
VDDINT |
111 |
BG |
140 |
D10 |
25 |
VDDEXT |
54 |
GND |
83 |
OPMODE |
112 |
BR |
141 |
D11 |
26 |
HACK |
55 |
GND |
84 |
A0 |
113 |
BMS |
142 |
D12 |
27 |
HCMS |
56 |
DT0 |
85 |
A1 |
114 |
IOMS |
143 |
VDDEXT |
28 |
HCIOMS |
57 |
TCLK0 |
86 |
A2 |
115 |
MS0 |
144 |
D13 |
29 |
GND |
58 |
VDDINT |
87 |
A3 |
116 |
MS1 |
|
|
–44– |
REV. A |
