Serial Peripheral Interface (SPI) Port—Slave Timing

Table 21 and Figure 22 describe SPI port slave operations.

Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter					Min	Max	Unit
Switching Characteristics
tDSOE	SPISS Assertion to Data Out Active				0	8	ns
tDSDHI	SPISS Deassertion to Data High Impedance				0	10	ns
tDDSPID	SCLK Edge to Data Out Valid (Data Out Delay)				0	10	ns
tHDSPID	SCLK Edge to Data Out Invalid (Data Out Hold)				0	10	ns
Timing Requirements
tSPICHS	Serial Clock High Period				2tHCLK		ns
tSPICLS	Serial Clock Low Period				2tHCLK		ns
tSPICLK	Serial Clock Period				4tHCLK		ns
tHDS	Last SPICLK Edge to SPISS Not Asserted				2tHCLK		ns
tSPITDS	Sequential Transfer Delay				2tHCLK +4		ns
tSDSCI	SPISS Assertion to First SPICLK Edge				2tHCLK		ns
tSSPID	Data Input Valid to SCLK Edge (Data Input Setup)				1.6		ns
tHSPID	SCLK Sampling Edge to Data Input Invalid (Data In Hold)				2.4		ns
	SPISS
(INPUT)
	tSPICHS		tSPICLS	tSPICLK	tHDS	tSPITDS
	SCLK
(CPOL = 0)
(INPUT)
	tSPICLS		tSPICHS
	tSDSCI
	SCLK
(CPOL = 1)
(INPUT)
	tDSOE	tDDSPID	tHDSPID	tDDSPID	tDSDHI
	MISO		MSB		LSB
(OUTPUT)			MSB		LSB
(OUTPUT)
CPHA = 1		tSSPID	tHSPID	tSSPID	tHSPID
		tSSPID	tHSPID	tSSPID	tHSPID
	MOSI	MSB			LSB
(INPUT)		VALID			VALID
	tDSOE	tDDSPID			tDSDHI
	MISO	MSB		LSB
(OUTPUT)		MSB		LSB
(OUTPUT)
CPHA = 0			tSSPID		tHSPID
	MOSI	MSB		LSB
(INPUT)		VALID		VALID

Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing

REV. A

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