External Port Write Cycle Timing

Parameter1, 2

Min

Max

Unit

Switching Characteristics

tCSWS

Chip Select Asserted to WR Asserted Delay

0.5tHCLK –4

ns

tAWS

Address Valid to WR Setup and Delay

0.5tHCLK –3

ns

tWSCS

WR Deasserted to Chip Select Deasserted

0.5tHCLK –4

ns

tWSA

WR Deasserted to Address Invalid

0.5tHCLK –3

ns

tWW

WR Strobe Pulsewidth

tHCLK –2+W3

ns

tCDA

WR to Data Enable Access Delay

0

ns

tCDD

WR to Data Disable Access Delay

0.5tHCLK –3

0.5tHCLK +4

ns

tDSW

Data Valid to WR Deasserted Setup

tHCLK +1+W3

tHCLK +7+W3

ns

tDHW

WR Deasserted to Data Invalid Hold Time; E_WHC4

3.4

ns

tDHW

WR Deasserted to Data Invalid Hold Time; E_WHC4

tHCLK +3.4

ns

tWWR

WR Deasserted to WR, RD Asserted

tHCLK

Timing Requirements

tAKW

ACK Strobe Pulsewidth

12.5

ns

tDWSAK

ACK Delay from WR Low

0

ns

1tHCLK is the peripheral clock period.

2These are timing parameters that are based on worst-case operating conditions.

3W = (number of waitstates specified in wait register) tHCLK.

4Write hold cycle–memory select control registers (MS CTL).

tC S W S

tW S C S

M S 3 – 0

IO M S

B M S

A 21–0

tA W S

tW W

tW S A

W R

tW W R

tD W S A K

tA K W

A C K

tC D D

tC D A

tD S W

tD H W

D 15–0

R D

–22–

REV. A