ADSP-2191M
External Port Bus Request and Grant Cycle Timing
Table 14 and Figure 13 describe external port bus request and bus grant operations.
Table 14. External Port Bus Request and Grant Cycle Timing
Parameter1, 2 |
|
Min |
Max |
Unit |
Switching Characteristics |
|
|
|
|
tSD |
CLKOUT High to xMS, Address, and RD/WR Disable |
|
0.5tHCLK +1 |
ns |
tSE |
CLKOUT Low to xMS, Address, and RD/WR Enable |
0 |
4 |
ns |
tDBG |
CLKOUT High to BG Asserted Setup |
0 |
4 |
ns |
tEBG |
CLKOUT High to BG Deasserted Hold Time |
0 |
4 |
ns |
tDBH |
CLKOUT High to BGH Asserted Setup |
0 |
4 |
ns |
tEBH |
CLKOUT High to BGH Deasserted Hold Time |
0 |
4 |
ns |
Timing Requirements |
|
|
|
|
tBS |
BR Asserted to CLKOUT High Setup |
4.6 |
|
ns |
tBH |
CLKOUT High to BR Deasserted Hold Time |
0 |
|
ns |
1tHCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
CLKOUT |
|
|
tBS |
tBH |
|
BR |
|
|
|
tSD |
tSE |
MS3--0 |
|
|
IOMS |
|
|
BMS |
|
|
|
tSD |
tSE |
A21–0 |
|
|
|
tSD |
tSE |
|
|
|
WR |
|
|
RD |
|
|
|
tDBG |
tEBG |
BG |
|
|
|
tDBH |
tEBH |
BGH |
|
|
Figure 13. External Port Bus Request and Grant Cycle Timing
–24– |
REV. A |