- •PERFORMANCE FEATURES
- •FUNCTIONAL BLOCK DIAGRAM
- •INTEGRATION FEATURES
- •SYSTEM INTERFACE FEATURES
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •DSP Core Architecture
- •DSP Peripherals Architecture
- •Figure 1. System Diagram
- •Memory Architecture
- •Figure 2. Memory Map
- •Internal (On-Chip) Memory
- •External (Off-Chip) Memory
- •External Memory Space
- •I/O Memory Space
- •Boot Memory Space
- •Interrupts
- •DMA Controller
- •Host Port
- •Host Port Acknowledge (HACK) Modes
- •Host Port Chip Selects
- •DSP Serial Ports (SPORTs)
- •Serial Peripheral Interface (SPI) Ports
- •UART Port
- •Programmable Flag (PFx) Pins
- •Low Power Operation
- •Idle Mode
- •Power-Down Core Mode
- •Power-Down Core/Peripherals Mode
- •Power-Down All Mode
- •Clock Signals
- •Figure 3. External Crystal Connections
- •Reset
- •Power Supplies
- •Power-Up Sequence
- •Booting Modes
- •Bus Request and Bus Grant
- •Instruction Set Description
- •Development Tools
- •Designing an Emulator-Compatible DSP Board (Target)
- •Target Board Header
- •Figure 4. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 5. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 6. JTAG Pod Connector Dimensions
- •Figure 7. JTAG Pod Connector Keep-Out Area
- •Design-for-Emulation Circuit Information
- •Additional Information
- •PIN FUNCTION DESCRIPTIONS
- •SPECIFICATIONS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •Power Dissipation
- •TIMING SPECIFICATIONS
- •Clock In and Clock Out Cycle Timing
- •Figure 8. Clock In and Clock Out Cycle Timing
- •Programmable Flags Cycle Timing
- •Figure 9. Programmable Flags Cycle Timing
- •Timer PWM_OUT Cycle Timing
- •Figure 10. Timer PWM_OUT Cycle Timing
- •External Port Write Cycle Timing
- •Figure 11. External Port Write Cycle Timing
- •External Port Read Cycle Timing
- •Figure 12. External Port Read Cycle Timing
- •External Port Bus Request and Grant Cycle Timing
- •Figure 13. External Port Bus Request and Grant Cycle Timing
- •Host Port ALE Mode Write Cycle Timing
- •Figure 14. Host Port ALE Mode Write Cycle Timing
- •Host Port ACC Mode Write Cycle Timing
- •Figure 15. Host Port ACC Mode Write Cycle Timing
- •Host Port ALE Mode Read Cycle Timing
- •Figure 16. Host Port ALE Mode Read Cycle Timing
- •Host Port ACC Mode Read Cycle Timing
- •Figure 17. Host Port ACC Mode Read Cycle Timing
- •Serial Ports
- •Figure 18. Serial Ports
- •Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5tSCLK)
- •Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5tHCLK)
- •Serial Peripheral Interface (SPI) Port—Master Timing
- •Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
- •Serial Peripheral Interface (SPI) Port—Slave Timing
- •Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
- •Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
- •Figure 23. UART Port—Receive and Transmit Timing
- •JTAG Test And Emulation Port Timing
- •Figure 24. JTAG Port Timing
- •Output Drive Currents
- •Figure 25. Typical Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Disable Time
- •Figure 26. Output Enable/Disable
- •Figure 27. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Figure 28. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
- •Output Enable Time
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Figure 30. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)
- •Environmental Conditions
- •Thermal Characteristics
- •144-Lead LQFP Pinout
- •144-Lead Mini-BGA Pinout
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
- •Revision History
ADSP-2191M
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
|
|
|
K Grade (Commercial) |
B Grade (Industrial) |
|
||
Parameter |
|
Test Conditions |
Min |
Max |
Min |
Max |
Unit |
|
|
|
|
|
|
|
|
VDDINT |
Internal (Core) Supply |
|
2.37 |
2.63 |
2.37 |
2.63 |
V |
|
Voltage |
|
|
|
|
|
|
VDDEXT |
External (I/O) Supply |
|
2.97 |
3.6 |
2.97 |
3.6 |
V |
|
Voltage |
|
|
|
|
|
|
VIH |
High Level Input Voltage |
@ VDDINT = max, |
2.0 |
VDDEXT +0.3 |
2.0 |
VDDEXT +0.3 |
V |
|
|
VDDEXT = max |
–0.3 |
+0.8 |
–0.3 |
+0.8 |
V |
VIL |
Low Level Input Voltage |
@ VDDINT = min, |
|||||
TAMB |
Ambient Operating |
VDDEXT = min |
0 |
70 |
–40 |
+85 |
ºC |
|
|||||||
|
Temperature |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Specifications subject to change without notice. |
|
|
|
|
|
|
|
ELECTRICAL CHARACTERISTICS
|
|
|
|
K and B Grades |
|
|
Parameter |
|
Test Conditions |
Min |
Typ |
Max |
Unit |
|
|
|
|
|
|
|
VOH |
High Level Output Voltage1 |
@ VDDEXT = min, |
2.4 |
|
|
V |
VOL |
Low Level Output Voltage1 |
IOH = –0.5 mA |
|
|
0.4 |
V |
@ VDDEXT = min, |
|
|
||||
IIH |
High Level Input Current2, 3 |
IOL = 2.0 mA |
|
|
10 |
µA |
@ VDDEXT = max, |
|
|
||||
IIL |
Low Level Input Current3, 4 |
VIN = VDD max |
|
|
10 |
µA |
@ VDDEXT = max, |
|
|
||||
IIHP |
High Level Input Current5 |
VIN = 0 V |
30 |
|
100 |
µA |
@ VDDEXT = max, |
|
|||||
IILP |
Low Level Input Current4 |
VIN = VDD max |
|
|
|
|
@ VDDEXT = max, |
20 |
|
70 |
µA |
||
IOZH |
Three-State Leakage Current5 |
VIN = 0 V |
|
|
10 |
µA |
@ VDDEXT = max, |
|
|
||||
IOZL |
Three-State Leakage Current6 |
VIN = VDD max |
|
|
10 |
µA |
@ VDDEXT = max, |
|
|
||||
CIN |
Input Capacitance6, 7 |
VIN = 0 V |
|
|
|
|
fIN = 1 MHz, |
|
|
8 |
pF |
||
|
|
TCASE = 25°C, |
|
|
|
|
|
|
VIN = 2.5 V |
|
|
|
|
Specifications subject to change without notice.
1Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH, BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1.
2Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P. 3Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET. 4Applies to input pin with internal pull-down: TRST.
5Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx, HAD15–0, TMR2–0.
6Applies to all signal pins.
7Guaranteed, but not tested.
–18– |
REV. A |