7.3.6 Concurrency

Verilog-AMS HDL provides synchronization between the continuous and discrete domains. Simulation in the discrete domain proceeds in integer multiples of the digital tick. This is the smallest value of the second argument of the `timescale directive (see 19.8 in IEEE std 1364-2005 Verilog HDL).

Simulation in the continuous domain appears to proceed continuously. Thus, there is no time granularity below which continuous values can be guaranteed to be constant.

The rest of this subclause describes synchronization semantics for each of the four types of mixed-signal behavioral interaction. Any synchronization method can be employed, provided the semantics preserved. A typical synchronization algorithm is described in 8.2.

7.3.6.1 Analog event appearing in a digital event control

In this case, an analog event, such as cross or timer, appears in an @() statement in the digital context.

Example:

always begin

@(cross(V(x) - 5.5,1)) n = 1;

end

Besides using analog event functions, one can also use analog variables that are only assigned values in analog event statements in a digital event control statement. An event occurs whenever a value is assigned to the variable, regardless of whether the variable changes value or not. This might be done when one wants to sample a value in the continuous time domain to avoid jitter being created by the discrete nature of time in the digital context, but wish to process the sample in the digital context.

Example:

analog @(timer(0,100n)) smpl = V(in);

always @(smpl) begin

...

When it is determined the event has occurred in the analog domain, the statements under the event control shall be scheduled in the digital domain at the nearest digital time tick to the time of the analog event. This event shall not be schedule in the digital domain earlier than the last or current digital event (see 8.2.3), however it may appear to be in a delta cycle belonging to a tick started at an earlier or later time.

Zero-delay scheduling is not rounded, so in the case where the digital event causes another event on the digital to analog boundary with zero delay, it will be handled at the current analog time.

7.3.6.2 Digital event appearing in an analog event control

Example:

analog begin @(posedge n)

r = 3.14;

end