Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)

do not cause extra distortion. In reality, the rise time and slew rate depends on the voltage step, and the transition is not linear.

The asymmetrical rise and fall times generate harmonics. If errors are symmetrical in the rising and falling edges and are proportional to the given step size, then errors do not generate harmonics. The asymmetrical switching in the rising and falling characteristics tends to generate even-order harmonics [Cro98]. The opposite-polarity glitch components on the rising and falling steps will tend to generate even-order harmonics (see Figure 10-9(j)).

10.7 Different Current Steering D/A Converters Architectures

The core of a current-steering D/A converter consists of an array of current sources that are switched to the output according to the digital input code. This can be accomplished in several ways, resulting in three different architectures that will be briefly discussed.

10.7.1 Binary Architecture

The easiest solution can be found by a binary switched D/A converter. In this case, each digital input directly controls the number unit current sources (proportional to bit weight) that have to be switched to the output (Figure 1013). This architecture can be implemented on a small silicon area and it minimizes the digital power consumption [Raz95], [Lin98], [Bos01]. The most significant bits control large currents that have to match the previous current with an accuracy of 0.5 LSB when the digital input value is increased by one. As the error is proportional to current, this becomes very hard to achieve. This can cause large DNL errors that lead to severe degradation of the static performance for this architecture.

The particular disadvantage of this architecture is glitches. The worst glitch in the output is most often found at the major carry of the D/A con-

dV dt

Figure 10-12. Constant rise time and slew rate.

verter (switching between 100…00 to 011…11). There will be a glitch in the output as each of the switches turn on and off at different times. The glitch is code dependent and thus produces harmonic distortion and even nonharmonic spurs. The current switches are usually size-scaled in binaryweighted design to account for the various current densities. So the parasitic capacitances are scaled by binary. This makes timing of the switches even harder.

10.7.2 Unary Architecture

In the unary architecture, the current source array consists of (2N -1) unity current sources that can be accessed separately (Figure 10-14). The digital input code has to be converted to a thermometer code that determines the number of current sources that have to be switched to the output. The decoder consumes a lot of silicon area and has a large power consumption but this architecture has a good DNL specification since only one extra unity current source has to be switched to the output when the digital output is increased by one. Because in this D/A converter all the switches change in the same direction with unary code, the output is always monotonic. The timing error is smaller than in the binary weighted D/A converter, because all the current switches are equally sized, so the switch drivers have the same load. The decoder logic high current consumption causes supply voltage variation, which increases glitches at the D/A converter output.

Perhaps more importantly, a D/A converter based on a thermometer code, rather than on binary weighted architecture, greatly minimizes glitches. This is due to the fact that only one switch changes its state when the binary code changes by one. It should also be mentioned here that latches could be used in the binary-to thermometer code conversion such that no glitches occur in the digital thermometer-code words and that pipelining can be also used to maintain a high throughput speed. All the current switches in a thermometercode approach are equal sizes, since they all pass equal currents.

Figure 10-13. A binary switched D/A converter.

follows during the transitions control voltage (not linearly), it is possible to reduce this variation by decreasing control voltage swing.

The problem with the control voltage swing reduction is that the switch driver current driving capability is decreased, thus the switches operation speed degrades. It is common to use cross-coupled or normal inverters, the power supply range of which is reduced [Bos98], [Bas98], [Bos01]. In NMOS current switches, if the positive supply voltage is set lower than the supply voltage, then the current switches are in the saturation region, and the negative voltage is the ground. The crosspoint of the control voltages must be set to a high level because the output voltage swing is minimized, and then voltage is near that at which the current sources transistors are in the saturation region. If the current switch need not operate in the saturation re-

VDD

(c) Edge delaying with two NAND gates.

Figure 10-17. Circuits for delaying control signal falling edge.

is that both switch driver buffers needs a two inverters chain, which easily destroy the differential output if their sizing is changed due to the process variations. By connecting cascade transistors biased in the saturation region between the buffer transistors and the output [Fal99], it is possible to reduce the extent to which the control signals of the inverter couple to the output with the penalty of reduced switching speed.

A differentially controlled version of the previous buffer pair is shown in Figure 10-19(b) [Mer00]. Because both buffers are steered with the same control signals, the transitions occur simultaneously. The problem in this topology is the limited possibility of adjusting the crosspoint; this is why the minimum value of the control signals should be set as high as possible, thus reducing the supply range, which degrades the operation speed.

A simple differential voltage swing restricting circuit is shown in Figure

10-20(a). The signals Vin and V in set if the output is connected to positive supply or the drain voltage of the diode connected transistor. The ability of the current to steer to negative directions is not great because there are two transistors in the current path, which raises the crosspoint of the control signals.

A switch driver in Figure 10-20(b) is a combination of the inverter and differential pair properties [Ded02]. It generates the switches difference voltage instead of two control voltages and follows the process variations at the switches difference voltage. In Figure 10-20(b), the current path is shown

in black, when Vin is off and V in is on. The transistors A and B are biased in the linear region, so that the node voltage between them keeps the transistor G at the saturation region. Furthermore, this voltage adjusts the transistor G source node voltage. The transistors A and B can be replaced with resistors,

VDD

Vbias1

A

Vbias2

B

X

Figure 10-20. Circuits for reducing control signals swing.

but, in the transistor implementations, the bias circuit can be used to assure that the voltage at node X follows the process variations in the threshold voltages of the switch transistors. The positive control voltage depends on the drain to source current of the transistors A, B and C. Because the current is generated by the transistors I and H (located near the current source matrix) in the same way as in the current switches, the negative voltage follows the process variation changes by altering the negative control voltage according to the current switch source voltage. The switch driver is fast because the drain to source voltage of the transistor G achieves its maximum voltage quickly due to the steep current to voltage curve of the transistor. Furthermore, the difference voltage could be set near the minimum voltage because the safety margin can be reduced due to the process variation compensation.

10.8.3 Current Switch Sizing

The control signals of the current switch coupling to the D/A converter output is related to the current switch gate capacitance [Tak91], Cg WL Therefore the size of the current switches should be minimized. If the current in the source is constant, then VGS ~ 1/sqrt(W). The source voltage of the current switches is the difference between the control voltage and VGS . When the size of the transistor is decreased, the required VGS grows so high that the current sources remain no longer in the saturation region. The control voltage should be increased or the output current decreased to keep the current sources in the saturation region. Both approaches increase distortions; increasing the control voltage might set the current switches in the linear region. The size of the current switches should be set so that the current sources drain to source voltage is above saturation voltage when the output voltage is at the minimum.

(a) Switches in linear region. (b) Switches in saturation region. Figure 10-21. Dummy switches.

10.8.4 Dummy Switches

Adding to the output equal but opposite sign glitch could compensate the glitch caused by the switch control signal feedthrough. If the current switches in the on-state are in the linear region, then the gate capacitance is divided approximately equally between the drain and source [All87]. The glitch due to the control signal feedthrough could be compensated by a dummy transistor, which has a size half of the switch transistor size and its source and drain connected together (Figure 10-21(a)) [Sch88]. The gate capacitance to the output is the same as that in the switch transistor. When the dummy switch is driven by the switch complementary control signals, the equal but opposite sign glitch cancels the original spike. In practice, the switches capacitance is not divided equally, and thus the cancellation is not perfect. If the glitches have a timing difference, there will be two glitches. Furthermore, the transistor cannot be minimum sized while the dummy transistors add capacitive load to the output, which makes the converter slower.

If the current switches in on state are in the saturation region, the gate capacitance to the output is the same as in the cut-off region [All87]. This being so, glitches could be compensated by adding equal sized dummy transistors parallel to current switches, so that dummy switches sources are crosscoupled and the drains are connected together (Figure 10-21(b)) [Luh00]. The dummy transistors are in the cut-off region, the voltage coupling from the gate to the output is complementary to the switches feedthrough. As above, the dummy switches increase output load capacitance and imperfect synchronization causes extra glitches.

10.8.5 Removing Spurs from Nyquist Band

The D/A converter spectrum is periodical with sampling frequency. The reconstructing filter must remove the images. Therefore the D/A converter spectral purity is important in the Nyquist band. If the glitches could be

Iout Iout

Vctrl

DEMUX

Vctrl

DEMUX

clk/2

clk/2

Figure 10-22. Current switches, which remove spurs from Nyquist band.