Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)

spur power is concentrated in one peak in Figure 8-2, because M is 2 (7.8). The worst-case carrier-to-spur level due to the phase truncation appears to be 44.24 dBc. The expect worst-case carrier-to-spur value is 44.17 dBc (7.29), which agrees closely. The frequency bin of the worst case spur in Figure 8-2 is 1784 (8 F(1)), where F(1) is from (7.25) and (7.26) and the DFT is calculated over eight DDS output periods (Pe). If M is larger than 2, the spur power is spread over many peaks (see Figure 8-3). The number of spurs is 15 from (7.8) in Figure 8-3 Since M = 16 for this case, the expected worst-case carrier-to-spur value is approximately 48.16 dBc (7.30). The worst-case car- rier-to-spur level due to the phase truncation appears to be 48.08 dBc.

7.2 Finite Precision of Sine Samples Stored in LUT

Finite quantization in the sine LUT values also leads to the DDS output spectrum impairments. If it is assumed that the phase truncation does not exist, then the output of the DDS is given by

where eA(n) is the quantization error due to the finite sine LUT data word. The sequence of the LUT quantization errors is periodic, repeating every Pe samples (4.4). There are two limiting cases, i.e. cases where the numerical period of the output sequence (Pe) is either long or short, to consider.

In the first case, the quantization error results in what appears to be a white noise floor, but is actually a "sea" of very finely spaced discrete spurs. The amplitude quantization errors can be assumed to be totally uncorrelated

and where m is the word length of the sine values stored in the sine LUT. Then the amplitude error power is [Ben48]

The signal power of the sine wave is

A2

PA (7.35)

2

where A is the amplitude of the sine wave. In the DDS literature, there is well-known formula for the signal to noise ratio due to the amplitude quantization (rounding)

where PA is A2/2 (sine wave power), PCA is A2 (quadrature wave power), A is 0.5 in (7.36) and the quantization power of the sine wave

Comparing (7.22) and (7.36), if k ≤ + 2, then the phase truncation dominates S/N, otherwise amplitude quantization. Due to the sine/cosine wave symmetry the error is also symmetric, therefore the spurs located at the even bin positions are zero for all phase increment words [Tie71] (Pe/2 spurs for cosine output and Pe/4 spurs for quadrature output, where the period of the DDS output (Pe) is from (4.4)). The cosine generated is real, so its power is equally divided into negative and positive frequency components. The quadrature output is complex, so its power is in one frequency component. Therefore, the amplitude quantization noise floor is from (7.36) for the cosine output and quadrature output

In the second case, there will be no quantization errors if the samples match exactly the quantization levels, e. g., f ut f/4. The assumption that the error is evenly distributed in one period is really not valid due to the shortness of the period. Assuming that the amplitude error gets its maximum absolute value (∆A/2) at every sampling instance, and that all the energy is in one spur, the carrier-to-spur ratio is

However, simulations indicate that in the worst-case the sum of the discrete spurs is approximately equal to

Figure 7-3. Time series vectors for a 3-bit phase accumulator for ∆P = 1 and ∆P = 3. The column vector for ∆P = 3 can be formed from a permutation of the values of the ∆P = 1 vector, regardless of the initial phase accumulator contents.

7.3 Distribution of Spurs

One of the advantages of a DDS is its ability to provide a continuous phase when changing phase increment words; the phase accumulator need not be reset when a new ∆P is applied. The state of the phase accumulator at the point in time when a new ∆P is applied provides a natural phase-offset for the subsequent DDS output, thereby providing continuous-phase frequency switching. The initial phase of the phase accumulator at the time when a new ∆P is applied could, however, also be a factor in determining the output spurs.

The j-bit phase accumulator can be considered as a permutation generator, where each value of ∆P provides a different permutation of the values from 0 to 2j - 1 given by

Figure 7.4. Time series vectors for a 3-bit accumulator for ∆P = 2 and ∆P = 6.

where WPe e j2 / Pe

and Pe is the period of the phase accumulator output (4.4). (7.46) can be used to show that permutation samples in the time domain produce the same type of permutation in the frequency domain by defining the new index

The above equation establishes that the permutation of the samples in the time domain results in the same type of permutation as the DFT samples in the frequency domain, because J and Pe are relatively prime. This means that the spurious spectrum due to all system non-linearities generated by the phase increment words with the property of GCD(∆P, 2j) = 2i is a permutation of the spectrum generated by ∆P = 2i (assuming the same initial phase, p = 0 in this case), because each spectrum will differ only in the position of the spurs and not in the magnitudes. Therefore, by evaluating the DDS spectrum for ∆P = 2i and every initial phase pi ɽ (0, ..., 2i – 1) with i ɽ (0, ..., j – 1), we know the DDS spectrum magnitude for any ∆P and initial phase p. For phase increment words with GCD(∆P, 2j) = 1, the DDS spectrum magnitude does not depend on the initial phase and the evaluation of the spectrum magnitude has to be made just for p = 0 (Figure 7-3).

Moreover, when the output of the phase accumulator is truncated to k bits (see Section 7.1), for phase increment words with GCD(∆P, 2j) = 2i 2j-k the least i significant bits of the initial phase p does not affect the output sequence. For the spectrum evaluation procedure, it means that for these phase increment words the DDS spectrum magnitude does not depend on the initial phase and the evaluation of the spectrum has to be made just for p = 0.

Two ∆P values 619 and 1121 are considered in the example. The DFT of the DDS output sequence for ∆P = 619 is shown in Figure 7-5, where the worst-case carrier-to-spur level due to the phase truncation appears to be

48.08 dBc. Since M >> 2 for this case, the expected worst-case carrier-to- spur value is 48.16 dBc (7.30), which agrees closely. The number of spurs in the figures is 15, from (7.8). The frequency bins of the spurs in Figure 7-5 could be calculated using (7.25) and (7.26). The DFT spectrum for the second frequency case of ∆P = 1121 is shown in Figure 7-6. As predicted, since

GCD (∆P, 2j) = 1 for this case as well, the worst-case carrier-to-spur level is unchanged and only the position of the spurs has been permutated.

7.4 Phase Noise of DDS Output

Leeson has developed a model that describes the origins of phase noise in oscillators [Lee66]; since it closely fits experimental data, the model is widely used in describing the phase noise of the oscillators [Roh83], [Man87]. In the model, the sampling clock signal (oscillator output) is phase modulated by a sine wave of frequency f

where is the sampling clock frequency of DDS, β is the maximum value of the phase deviation, is the offset frequency. The spectrum of the sampling clock signal is shown in Figure 7-7.

The frequency of the sampling clock signal is

The DDS could be described as a frequency divider, and so the output frequency of the DDS is

where j is the word length of the DDS phase accumulator, ∆P is the phase increment word, N is the division ratio. The phase of the DDS output is

Comparing (7.52) and (7.56), the modulation index is changed from β to β/N, but the offset frequency is not changed. The spectrum of the DDS sampling clock is given by inspection from the equivalent relationship

where Ji(β) are Bessel functions of the first kind. The spectrum of the DDS output is given by inspection from the equivalent relationship

The relative power of the DDS output phase noise at offset i m is from (7.57) and (7.58)

Figure 7-7. Typical phase noise sidebands of an oscillator.

From the above equation, it can be seen that the relative power level of the DDS output phase noise depends on the ratio between the output frequency and sampling clock frequency. The output signal will exhibit the improved phase noise performance [Jen97], [Ana99]

f

nclk 20 log10 ( f s ). (7.61)

out

The DDS circuitry has a noise floor, which, at some point, will limit this improvement. An output phase noise floor of -160 dBc/Hz is possible, depending on the logic family used to implement the DDS [Qua90]. The frequency accuracy of the sampling clock is propagated through the DDS [Qua90]. Therefore, if the sampling clock frequency is 0.1 PPM higher than desired, the output frequency will be also higher by 0.1 PPM.

7.5 Post-Filter Errors

The sixth source of noise at the DDS output is the post-filter, eF, which is

needed to remove the high frequency sampling components. Since this postfilter is an energy storage device, the problem of the response time arises. The filter must have a very flat amplitude response and a constant group delay across the bandwidth of interest so that the perfectly linear digital modulation and frequency synthesis advantages are not lost. The output filter also affects the switching time of the DDS output.

REFERENCES

[Ana99] Analog Devices, "A Technical Tutorial on Digital Signal Synthesis," Application Note, 1999.

[Ben48] W. R. Bennett, "Spectra of Quantized Signals," Bell Sys. Tech. J., Vol. 27, pp. 446-472, July 1948.