Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)
.pdfContents |
xi |
12. RE-SAMPLING................................................................ |
239 |
12.1 Interpolation for Timing Adjustment ........................................... |
240 |
12.2Interpolation Filter with Polynomial-Based Impulse Response..241
12.2.1 Lagrange Interpolation ...................................................................... |
242 |
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12.3 |
Farrow Structure ............................................................................ |
243 |
12.4 |
Alternative Polynomial Interpolators ........................................... |
246 |
12.5 |
Calculation of Fractional Interval k Using NCO ........................ |
250 |
12.5.1 Synchronization of Resampling NCO ............................................... |
252 |
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12.5.2 Simulations........................................................................................ |
255 |
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REFERENCES........................................................................... |
255 |
13.FIR FILTERS FOR COMPENSATING D/A
CONVERTER FREQUENCY RESPONSE DISTORTION...... |
259 |
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13.1 |
Four Different D/A Converter Pulse Shapes ................................ |
262 |
13.2 |
Different Implementation............................................................... |
264 |
13.3 |
Filter Design .................................................................................... |
266 |
13.4 |
Implementations.............................................................................. |
266 |
13.5 |
Measurement Result....................................................................... |
267 |
13.6 |
Conclusion ....................................................................................... |
267 |
REFERENCES........................................................................... |
267 |
14.A DIRECT DIGITAL SYNTHESIZER WITH
TUNABLE DELTA SIGMA MODULATOR .............................. |
269 |
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14.1 |
Direct Digital Synthesizer with Tunable ∆¦ Modulator ............. |
270 |
14.2 |
Quadrature Modulator................................................................... |
271 |
14.3 |
Phase to Amplitude Converters..................................................... |
272 |
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C ontents |
14.4 |
Tunable ∆¦ Modulators |
.................................................................274 |
14.5 |
1-bit D/A Converter........................................................................ |
275 |
14.6 |
Implementations.............................................................................. |
276 |
14.7 |
Measurement Results ..................................................................... |
276 |
14.8 |
Conclusions...................................................................................... |
277 |
REFERENCES........................................................................... |
277 |
15.A DIGITAL QUADRATURE MODULATOR WITH
ON-CHIP D/A CONVERTER....................................................... |
279 |
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15.1 |
Multiplier Free Quadrature Modulation...................................... |
280 |
15.2 |
Interpolation Filters........................................................................ |
281 |
15.3 |
D/A Converter................................................................................. |
283 |
15.4 |
Implementation and Layout........................................................... |
285 |
15.5 |
On-chip Capacitor .......................................................................... |
286 |
15.5.1 Analytic First Order Model ............................................................... |
287 |
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15.5.2 Negative Feedback ............................................................................ |
287 |
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15.5.3 Reducing di/dt Noise......................................................................... |
288 |
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15.5.4 Decoupling Capacitance.................................................................... |
289 |
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15.5.5 Resonance and Damping ................................................................... |
289 |
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15.5.6 Implemented On-chip Capacitor ....................................................... |
292 |
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15.6 |
Measurement Results ..................................................................... |
293 |
15.7 |
Conclusion ....................................................................................... |
294 |
REFERENCES........................................................................... |
295 |
16.A GSM/EDGE/WCDMA MODULATOR WITH ON-
CHIP D/A CONVERTER FOR BASE STATIONS .................... |
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16.1 Supported Communication Standards.......................................... |
297 |
16.1.1 GSM System...................................................................................... |
298 |
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16.1.2 EDGE System.................................................................................... |
300 |
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16.1.3 WCDMA System .............................................................................. |
304 |
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16.2 |
GSM/EDGE/WCDMA Modulator ................................................ |
305 |
16.3 |
Pulse Shaping and Half-band Filters ............................................ |
306 |
16.4 |
Re-Sampler...................................................................................... |
307 |
16.5 |
CORDIC Rotator............................................................................ |
308 |
16.6 |
Ramp Generator and Output Power Level Controller................ |
309 |
16.6.1 Ramp Generator ................................................................................ |
310 |
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16.6.2 Initial Values of Ramp Generator...................................................... |
310 |
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16.6.3 Parallel Structure ............................................................................... |
311 |
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16.7 |
Multicarrier Modulator Architectures ......................................... |
312 |
16.8 |
Design Flow ..................................................................................... |
313 |
16.8.1 High Level Modeling ........................................................................ |
314 |
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16.8.2 Hardware Description........................................................................ |
314 |
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16.8.3 Logic Synthesis ................................................................................. |
314 |
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16.8.4 Layout Synthesis ............................................................................... |
315 |
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16.8.5 Final Layout ...................................................................................... |
315 |
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16.9 |
D/A Converter................................................................................. |
319 |
16.10 |
Measurement Results ..................................................................... |
320 |
16.11 |
Conclusions...................................................................................... |
322 |
REFERENCES........................................................................... |
323 |
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17. EFFECT OF CLIPPING IN WIDEBAND CDMA |
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SYSTEM AND SIMPLE ALGORITHM FOR PEAK |
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WINDOWING................................................................................. |
327 |
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17.1 |
Introduction..................................................................................... |
327 |
17.2 |
Clipping Methods............................................................................ |
328 |
17.2.1 Baseband Clipping ............................................................................ |
328 |
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17.2.2 Adaptive Baseband Clipping............................................................. |
328 |
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17.2.3 IF Clipping ........................................................................................ |
329 |
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17.2.4 Windowing Algorithm |
.......................................................................329 |
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17.3 |
Simulation Model............................................................................ |
332 |
17.4 |
Results.............................................................................................. |
333 |
17.4.1 Single Carrier .................................................................................... |
333 |
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17.4.2 Multicarrier........................................................................................ |
336 |
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17.5 |
Conclusions...................................................................................... |
337 |
REFERENCES........................................................................... |
337 |
18.REDUCING PEAK TO AVERAGE RATIO OF
MULTICARRIER GSM AND EDGE SIGNALS........................ |
339 |
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18.1 |
Introduction..................................................................................... |
339 |
18.2 |
Signal Model.................................................................................... |
340 |
18.3 |
Clipping Methods............................................................................ |
341 |
18.4 |
Results.............................................................................................. |
342 |
18.4.1 GSM .................................................................................................. |
342 |
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18.4.2 EDGE ................................................................................................ |
344 |
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18.4.3 GSM/EDGE ...................................................................................... |
345 |
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18.5 |
Conclusions...................................................................................... |
345 |
REFERENCES........................................................................... |
346 |
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ADDITIONAL REFERENCES TO CLIPPING .................... |
347 |
19.APPENDIX: DERIVATION OF THE LAGRANGE
INTERPOLATOR .......................................................................... |
353 |
INDEX......................................................................................... |
355 |
Acknowledgements
A significant part of this work was conducted during project-work funded by the Technology Development Center (Tekes) and the Academy of Finland. Personal grants were received from the Nokia Foundation, Jenny and Antti Wihuri Foundation, and the Electronic Engineering Foundation. I would like to acknowledge my sincere gratitude to Jaakko Ketola, Marko Kosunen, Jonne Lindeberg, Johan Sommarek, Ilari Teikari and Olli Väänänen for generously providing assistance during the development of the material presented in this book.
Preface
The approach adopted in this book will, it is hoped, provide an understanding of key areas in the field of digital synthesizers and transmitters. It is easy to include different digital techniques in the digital synthesizers and transmitters by using digital signal processing methods, because the signal is in digital form. By programming the digital synthesizers and transmitters, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. Techniques such as digital predistortion for power amplifier linearization, digital compensation methods for analog I/Q modulator nonlinearities and digital power control and ramping are presented in this book. The flexibility of the digital synthesizers and transmitters makes them ideal as signal generators for software radio. Software radios represent a major change in the design paradigm for radios in which a large portion of the functionality is implemented through programmable signal processing devices, giving the radio the ability to change its operating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency (RF) and other analog components of traditional radios and emphasizes digital signal processing to enhance overall transmitter flexibility. Software radios are emerging in commercial and military infrastructure. This growth is motivated by the numerous advantages of software radios, such as the following:
1. Ease of design—Traditional radio design requires years of experience and great care on the part of the designer to understand how the various system components work in conjunction with one another. The time required to develop a marketable product is a key consideration in modern engineering design, and software radio implementations reduce the design cycles for new products, freeing the engineer from much of the iteration associated with
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analog hardware design. It is possible to design many different radio products using a common RF front-end with the desired frequency and bandwidth in conjunction with a variety of signal processing software.
2.Ease of manufacture—No two analog components have precisely identical performance; this necessitates rigorous quality control and testing of radios during the manufacturing process. However, given the same input, two digital processors running the same software will produce identical outputs. The move to digital hardware thus reduces the costs associated with manufacturing and testing the radios.
3.Multimode operation—the explosive growth of wireless has led to a proliferation of transmission standards; in many cases, it is desirable that a radio operates according to more than one standard.
4.Use of advanced signal processing techniques—the availability of high speed signal processing on board allows the implementation of new transmitter structures and signal processing techniques. Techniques such as digital predistortion for power amplifier linearization, digital compensation methods for analog I/Q modulator errors and digital power control and ramping, previously deemed too complex, are now finding their way into commercial systems as the performance of digital signal processors continues to increase.
5.Flexibility to incorporate additional functionality—Software radios may be modified in the field to correct unforeseen problems or upgrade the radio.
Figure 1 shows a block diagram of the conventional digital modulator. It consists of the following blocks: clipping circuit (Chapter 17 and Chapter 18), pulse shaping filters (Chapter 11), interpolation filters (Chapter 11), resamplers (Chapter 12), quadrature direct digital synthesizer (Chapters 4, 7, 8 and 9), inverse sinc filter (Chapter 13) and D/A converter (Chapter 10). The
QUADRATURE
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Figure 1 Digital modulator.
Preface |
xix |
alternative method of translating the baseband-centered spectrum to a programmable carrier center frequency is to use the CORDIC rotator (Chapter 6) instead of the quadrature direct digital synthesizer, two mixers and an adder. Three design examples of the digital modulator are presented (Chapters 14, 15 and 16).
Chapter 1 provides a basic introduction to transmitter architectures. The classic transmitter architecture is based upon linear power amplifiers and power combiners. Most recently, transmitters have been based upon a variety of different architectures including Envelope Elimination and Restoration (EER), polar loop, LInear amplification with Nonlinear Components (LINC), Combined Analogue Locked Loop Universal Modulator (CALLUM), LInear amplification employing Sampling Techniques (LIST) and transmitters based on bandpass sigma delta modulators.
Power amplifier linearization techniques are used both to improve linearity and to allow more efficient, but less linear, methods of operation. The three principal types of linearization are feedback, feedforward and predistortion. The combination of digital signal processing (DSP) and microprocessor control allows a widespread use of complicated feedback and predistortion techniques to improve power amplifier efficiency and linearity, as shown in Chapter 2.
In Chapter 3, methods and algorithms to compensate analog modulator errors are reviewed, while in Chapter 4, a description of the conventional direct digital synthesizer (DDS) is given. It is easy to include different modulation capabilities in DDSs by using digital signal processing methods, because the signal is in digital form. By programming the DDSs, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The digital circuits used to implement signal-processing functions do not suffer the effects of thermal drift, aging and component variations associated with their analog counterparts. The flexibility of the DDSs makes them ideal as signal generator for software radios. Recursive sinusoidal oscillators are presented in Chapter 5.
In Chapter 6, it is seen that circular rotation can be implemented efficiently using the CORDIC algorithm, an iterative algorithm for computing many elementary functions. The CORDIC algorithm is studied in detail. The finite word length effects in the CORDIC algorithm are investigated. Redundant implementations of the CORDIC rotator are overviewed and the hybrid CORDIC algorithms are reviewed.
The DDS is shown to produce spurs (spurious harmonics), as well as the desired output frequency, in Chapter 7. Different noise and spur sources are studied in detail. In Chapter 8, a study is made of how additional digital techniques (for example, dithering, error feedback methods) may be incorporated in the DDS in order to reduce the presence of spurious signals at
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the DDS output. The spur reduction techniques used in the sine output direct digital synthesizers are reviewed.
In Chapter 9, an investigation into the blocks of the DDS, namely a phase accumulator, a phase to amplitude converter (conventionally a sine ROM) and a filter, is carried out. Different techniques used to accelerate the operation speed of the phase accumulator are considered. Different sine memory compression and algorithmic techniques and their trade-offs are investigated.
D/A converters, along with the power amplifier, are the most critical components in software radio transmitters. Unfortunately, the development of D/A converters does not keep up with the capabilities of digital signal processing utilizing faster technologies. The different techniques used to enhance D/A converter static and dynamic performance are reviewed in Chapter 10.
The pulse shaping and interpolation filters are the topic of Chapter 11. Different methods of designing the pulse shaping filters are reviewed. The multirate signal processing is particularly important in software radio transmitters, where sample rates are low initially and must be increased for efficient subsequent processing.
The multi-standard modulator has to be able to accept data with different symbol rates. This fact leads to the need for a re-sampler that performs a conversion between variable sampling frequencies. There are several methods of realizing the re-sampler with an arbitrary sampling rate conversion. In Chapter 12, the design of the polynomial-based interpolation filter using the Lagrange method is presented. Some other polynomial-based methods are also discussed.
Three different designs to compensate the sinc(x) frequency response distortion resulting from D/A converters by using digital FIR filters are represented in Chapter 13. The filters are designed to compensate the signal’s second image distortion.
The design and implementation of a DDS with the tunable (real or complex) 1-bit ∆¦ D/A converter are described in Chapter 14. Since the 1-bit ∆¦ D/A converter has only one bit, the glitch problems and resulting spurious noise resulting from the use of the multi-bit D/A converter are avoided.
In traditional transmit solutions, a two-stage upconversion is performed in which a complex baseband signal is digitally modulated to the first IF (intermediate frequency) and then mixed to the second IF in the analog domain. The first analog IF mixer stage of the transmitter can be replaced with this digital quadrature modulator, as shown in Chapter 15.
In Chapter 16, the digital IF modulator is designed using specifications related to GSM, EDGE and WCDMA standards. By programming a GSM/EDGE/WCDMA modulator, different carrier spacings, modulation schemes, power ramping, frequency hopping and symbol rates can be
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achieved. By combining the outputs of multiple modulators, multicarrier signals can be formed or the modulator chips can be used for steering a phased array antenna. The formation of multi-carrier signals in the modulator increases the base station capacity
In a WCDMA system, the downlink signal typically has a high Peak to Average Ratio (PAR). In order to achieve a good efficiency in the power amplifier, the PAR must be reduced, i.e. the signal must be clipped. In Chapter 17, the effects of several different clipping methods on Error Vector Magnitude (EVM), Peak Code Domain Error (PCDE) and Adjacent Channel Leakage power Ratio (ACLR) are derived through simulations. A very straightforward algorithm for implementing a peak windowing clipping method is also presented.
In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital domain. The major drawback of combining digital carriers is a strongly varying envelope of the composite signal. The high PAR sets strict requirements for the linearity of the power amplifier. High linearity requirements for the power amplifier lead to low power efficiency and therefore to high power consumption. In Chapter 18, the possibility of reducing the PAR by clipping is investigated in two cases, GSM and EDGE.