- •Introduction to Digital Integrated Circuit Design
- •Aims and Objectives
- •Course Outline
- •Recommended Books
- •Supporting Material
- •Design Project
- •Assessment
- •Based on slides/material by…
- •Recommended Reading
- •Outline
- •Integrated Circuits
- •A Brief History
- •History of Integration
- •History of Technology
- •IP based SoC Design
- •Annual Sales
- •Any Device, Any Time, Anywhere
- •Outline
- •Implementation Methodologies
- •Full-custom
- •Custom Design - Layout
- •Standard-Cell–Based ICs
- •Full-custom Standard Cell
- •Routing a Standard Cell-based IC
- •Standard Cell Libraries
- •Macrocell-Based Design
- •Macrocell-Based Design Example
- •Gate-Array–Based ICs
- •Gate-Array–Based ICs (con’t)
- •Gate Array Approach - Example
- •Prewired Arrays
- •Programmable Logic Devices
- •EPLD Block Diagram
- •Field-Programmable Gate Arrays Fuse-based
- •Interconnect
- •Field-Programmable Gate Arrays RAM-based
- •RAM-based FPGA Basic Cell (CLB)
- •Outline
- •Design Abstraction Levels
- •ASIC Design Flow
- •ASIC Design Flow (con’t)
- •Outline
- •Moore’s Law
- •Moore’s Law – Intel Microprocessors
- •Evolution in Complexity
- •Scaling
- •Scaling Implications
- •Performance Improvement
- •Cost Improvement
- •Interconnect Woes
- •Reachable Radius
- •Dynamic Power
- •Static Power
- •Productivity
- •Very Few Companies Can Design High-End ICs
- •Less First Silicon Success and the Changing Rate of Failures
- •Physical Limits
- •Outline
- •Integrated Circuits Economics
- •Non-Recurring Engineering Costs (NRE)
- •Recurring Costs
- •Fixed Cost
- •New IC Design is Fairly Capital Intensive
- •Cost Breakdown
- •Outline
- •Silicon in 2010
- •ITRS
- •Summary
- •Journals and Conferences
- •Further Reading
Integrated Circuits Economics
Selling price Stotal
•Stotal = Ctotal / (1-m)
m = profit margin
Ctotal = total cost
•Nonrecurring engineering cost (NRE)
•Recurring cost
•Fixed cost
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 61 |
Non-Recurring Engineering Costs (NRE)
Engineering cost
•Depends on size of design team
•Include benefits, training, computers
•CAD tools:
ÊDigital front end: $10K
ÊAnalog front end: $100K
ÊDigital back end: $1M
Prototype manufacturing
•Mask costs: $500k – 1M in 130 nm process
•Test fixture and package tooling
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 62 |
Recurring Costs
Fabrication
•Wafer cost / (Dice per wafer * Yield)
•Wafer cost: $500 - $3000
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Dice per wafer: |
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r |
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2r |
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N =π |
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A |
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Yield: Y = e-AD |
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2A |
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Ê For small A, Y ≈ 1, cost proportional to area
Ê For large A, Y → 0, cost increases exponentially
Packaging
Test
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 63 |
Fixed Cost
Data sheets and application notes
Marketing and advertising
Yield analysis
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 64 |