- •Introduction to Digital Integrated Circuit Design
- •Aims and Objectives
- •Course Outline
- •Recommended Books
- •Supporting Material
- •Design Project
- •Assessment
- •Based on slides/material by…
- •Recommended Reading
- •Outline
- •Integrated Circuits
- •A Brief History
- •History of Integration
- •History of Technology
- •IP based SoC Design
- •Annual Sales
- •Any Device, Any Time, Anywhere
- •Outline
- •Implementation Methodologies
- •Full-custom
- •Custom Design - Layout
- •Standard-Cell–Based ICs
- •Full-custom Standard Cell
- •Routing a Standard Cell-based IC
- •Standard Cell Libraries
- •Macrocell-Based Design
- •Macrocell-Based Design Example
- •Gate-Array–Based ICs
- •Gate-Array–Based ICs (con’t)
- •Gate Array Approach - Example
- •Prewired Arrays
- •Programmable Logic Devices
- •EPLD Block Diagram
- •Field-Programmable Gate Arrays Fuse-based
- •Interconnect
- •Field-Programmable Gate Arrays RAM-based
- •RAM-based FPGA Basic Cell (CLB)
- •Outline
- •Design Abstraction Levels
- •ASIC Design Flow
- •ASIC Design Flow (con’t)
- •Outline
- •Moore’s Law
- •Moore’s Law – Intel Microprocessors
- •Evolution in Complexity
- •Scaling
- •Scaling Implications
- •Performance Improvement
- •Cost Improvement
- •Interconnect Woes
- •Reachable Radius
- •Dynamic Power
- •Static Power
- •Productivity
- •Very Few Companies Can Design High-End ICs
- •Less First Silicon Success and the Changing Rate of Failures
- •Physical Limits
- •Outline
- •Integrated Circuits Economics
- •Non-Recurring Engineering Costs (NRE)
- •Recurring Costs
- •Fixed Cost
- •New IC Design is Fairly Capital Intensive
- •Cost Breakdown
- •Outline
- •Silicon in 2010
- •ITRS
- •Summary
- •Journals and Conferences
- •Further Reading
Very Few Companies Can Design High-End ICs
Design productivity gap
10,000 |
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1,000 |
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Logic transistors per |
100 |
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Gap |
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chip |
10 |
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IC capacity |
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(in millions) |
1 |
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0.1 |
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productivity |
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0.01 |
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0.001 |
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1981 |
1983 |
1985 |
1987 |
1989 |
1991 |
1993 |
1995 |
1997 |
1999 |
2001 |
2003 |
2005 |
2007 |
2009 |
Designer productivity growing at slower rate
Ê1981: 100 designer months Æ ~$1M
Ê2002: 30,000 designer months Æ ~$300M
100,000 |
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10,000 |
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1000 |
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100 |
Productivity |
10 |
(K) Trans./Staff-Mo. |
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1 |
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0.1
0.01Source: ITRS’99
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 57 |
Less First Silicon Success and the Changing Rate of Failures
Increasing are Trends
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Logic/Functional |
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45% |
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62% |
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Noise / SI |
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10% |
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28% |
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First silicon success rates |
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Pow er Consumption |
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8% |
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22% |
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13% |
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Better |
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Clocking |
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18% |
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declining |
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• |
Functional Verification |
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Fast Path |
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17% |
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• |
First Silicon OK |
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• |
Noise / SI |
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Slow Path |
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48% in 2000 |
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16% |
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• |
39%Clocking2002 |
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Analog Tuning |
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23% |
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• |
34% in 2003 |
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14% |
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IR Drops |
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9% |
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IR Drops |
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14% |
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• |
Third Silicon OK |
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Worse |
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Yield / Reliability |
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• |
>90% in 2000 |
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12% |
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>70%AnaloginTuning2002 |
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Firmw are |
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10% |
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• |
>60% in 2003 |
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Mixed-Signal |
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Mixed-Signal Interface |
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14% |
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• |
DFM (RET) |
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5% |
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Interface |
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Other |
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4% |
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2003 |
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Collett International Research: |
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3% |
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2001 |
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RET |
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2000, 2002 Functional Verification Studies; |
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0% |
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2003 Design Closure Study, 01/04 |
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0% |
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10% |
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20% |
30% |
40% |
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50% |
60% |
70% |
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Trends are Decreasing
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 58 |
Physical Limits
Will Moore’s Law run out of steam?
•Can’t build transistors smaller than an atom…
Many reasons have been predicted for end of scaling
•Dynamic power
•Subthreshold leakage, tunneling
•Short channel effects
•Fabrication costs
•Electromigration
•Interconnect delay
Rumors of demise have been exaggerated
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 59 |
Outline
History
Implementation methodologies
Design flow
Technology scaling
VLSI/IC economics
Future trends
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 60 |