Field-Programmable Gate Arrays RAM-based
|
|
CLB |
CLB |
switching matrix
Horizontal routing channel
Interconnect point
CLB |
CLB |
Vertical routing channel
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 37 |
RAM-based FPGA Basic Cell (CLB)
Combinational logic
A
Any function of up to B/Q1/Q2 4 variables
C/Q1/Q2 D
A
Any function of up to B/Q1/Q2 4 variables
C/Q1/Q2 D
E
|
|
Storage elements |
|
|
R |
|
|
|
Din |
R |
|
F |
F |
D Q1 |
|
G |
|
|
|
|
|
F |
|
|
|
CE |
G
R
F D Q2
G
CE G
Clock
CE
Courtesy of Xilinx
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 38 |
Outline
History
Implementation methodologies
Design flow
Technology scaling
VLSI/IC economics
Future trends
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 39 |
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
|
DEVICE |
|
G |
S |
D |
n+ |
n+ |
Introduction & Trends |
Introduction to Digital Integrated Circuit Design |
Lecture 1 - 40 |