- •FEATURES
- •APPLICATIONS
- •DESCRIPTION
- •ABSOLUTE MAXIMUM RATINGS
- •PACKAGE DISSIPATION RATINGS
- •RECOMMENDED OPERATING CONDITIONS
- •ELECTRICAL CHARACTERISTICS: VDD = +5 V
- •ELECTRICAL CHARACTERISTICS: VDD = +2.7V
- •ELECTRICAL CHARACTERISTICS
- •PIN CONFIGURATIONS
- •TIMING INFORMATION
- •TYPICAL CHARACTERISTICS: VDD = +5V
- •TYPICAL CHARACTERISTICS: VDD = +2.7V
- •THEORY OF OPERATION
- •ANALOG INPUT
- •REFERENCE INPUT
- •NOISE
- •AVERAGING
- •DIGITAL INTERFACE
- •SIGNAL LEVELS
- •SERIAL INTERFACE
- •DATA FORMAT
- •POWER DISSIPATION
- •SHORT CYCLING
- •LAYOUT
- •APPLICATION CIRCUITS
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AVERAGING
The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results will reduce the transition noise from ±0.5LSB to ±0.25LSB. Averaging should only be used for input signals with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio will improve 3dB.
DIGITAL INTERFACE
SIGNAL LEVELS
The ADS8325 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range will accommodate different logic levels.
When the ADS8325'spower-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8325 can be connected directly to another 5V CMOS integrated circuit.
Another possibility is that the ADS8325's power-supply voltage is in the range of 2.7V to 3.6V. The ADS8325 can be connected directly to another 3.3V LVCMOS integrated circuit.
ADS8325
SBAS226C –MARCH 2002 –REVISED AUGUST 2007
SERIAL INTERFACE
The ADS8325 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Information section. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit.
A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format.
After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS8325 is in Straight Binary format (see Figure 36. This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise.
Copyright © 2002–2007, Texas Instruments Incorporated |
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19 |
Product Folder Link(s): ADS8325
ADS8325
www.ti.com
SBAS226C –MARCH 2002 –REVISED AUGUST 2007
Straight Binary
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1111 1111 1111 1111 |
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65535 |
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1111 1111 1111 1111 |
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65534 |
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1111 1111 1111 1111 |
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65533 |
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Code |
1000 0000 0000 0001 |
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32769 |
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DigitalOutput |
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1000 0000 0000 0000 |
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32768 |
Step |
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0111 1111 1111 1111 |
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32767 |
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0000 0000 0000 0010 |
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2 |
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0000 0000 0000 0001 |
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1 |
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0000 0000 0000 0000 |
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0 |
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VZ = VCM = 0V |
2.499962V |
2.500038V |
VFS = VCM + VREF = 5V |
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38.15µV |
VMS = VCM + VREF/2 = 2.5V |
VFS − 1LSB = 4.999924V |
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76.29µV |
Unipolar Analog Input Voltage |
4.999847V |
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152.58µV |
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1LSB = 76.29µV |
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VCM = 0V |
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16-BIT |
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VREF = 5V |
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Straight Binary Output |
Unipolar Analog Input |
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Zero Code |
VZ = 0000H |
VCODE = VCM |
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Midscale Code |
VMS = 8000H |
VCODE = VCM + VREF/2 |
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Full-Scale Code |
VFS = FFFFH |
VCODE = (VCM + VREF) − 1LSB |
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Figure 36. Ideal Conversion Characteristics (Condition: VCM = 0V, VREF = 5V)
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Copyright © 2002–2007, Texas Instruments Incorporated |
Product Folder Link(s): ADS8325