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ADC141S626

www.ti.com

SNAS434B –NOVEMBER 2007 –REVISED MARCH 2013

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter

Check for Samples: ADC141S626

FEATURES

True Differential Inputs

Guaranteed Performance from 50 kSPS to 250 kSPS

External Reference

Zero-Power Track Mode

Wide Input Common-Mode Voltage Range

Operating Temperature Range of −40°C to +85°C

SPI™ /QSPI™ /MICROWIRE/DSP Compatible Serial Interface

APPLICATIONS

DESCRIPTION

The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA. It also features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage.

Automotive Navigation

Portable Systems

Medical Instruments

Instrumentation and Control Systems

Motor Control

Direct Sensor Interface

KEY SPECIFICATIONS

Conversion Rate: 50 kSPS to 250 kSPS

INL: ± 0.95 LSB (Max)

DNL: ± 0.95 LSB (Max)

SNR: 82 dBc (Max)

THD: -90 dBc (Typ)

ENOB: 13.3 Bits(Min)

Power Consumption:

200 kSPS, 3V: 2.0 mW (Typ)

250 kSPS, 5V: 4.8 mW (Typ)

Power-Down, 3V: 4 µ W (Typ)

Power-Down, 5V: 13 µ W (Typ)

The serial data output is binary 2's complement and is compatible with several standards, such as SPI™ , QSPI™ , MICROWIRE, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress; thus, ADC141S626 has no latency.

The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VA of 5V while communicating with a 3V controller on the digital side. With a 3V source, the power consumption when operating at 200 kSPS is 2.0 mW. With a 5V source, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition (power-down) mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications.

Operation is guaranteed over the temperature range of −40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead VSSOP package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

 

Instruments standard warranty. Production processing does not

 

necessarily include testing of all parameters.

 

ADC141S626

SNAS434B –NOVEMBER 2007 –REVISED MARCH 2013

 

 

 

 

 

www.ti.com

Connection Diagram

 

 

 

 

 

 

VREF

 

 

 

 

 

 

 

 

1

10

 

VA

 

 

+IN

 

2

9

 

VIO

 

 

- IN

 

3

ADC141S626 8

 

SCLK

 

 

GND

 

4

7

 

DOUT

 

 

GND

 

5

6

 

 

 

 

 

 

CS

 

 

 

 

 

 

 

 

 

 

Block Diagram

 

 

VREF

 

 

 

 

 

 

 

 

 

 

 

 

SAR

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SERIAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERFACE

 

 

 

+IN

 

 

 

 

CDAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S/H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-IN

 

 

 

 

 

 

 

 

 

 

COMPARATOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

 

 

 

 

 

 

 

Pin No.

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

1

VREF

input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.

A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µFcapacitor is

 

 

 

 

 

 

 

 

recommended for enhanced performance.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

+IN

Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the

ADC141S626.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

−IN

Inverting Input. −IN is the negative analog input for the differential signal applied to the

ADC141S626.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

GND

Ground. GND is the ground reference point for all signals applied to the ADC141S626.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

GND

Ground. GND is the ground reference point for all signals applied to the ADC141S626.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Select Bar.

 

must be active LOW during an SPI conversion, which begins on the

 

 

 

 

 

 

 

 

CS

6

 

CS

 

falling edge of CS. The ADC141S626 is in acquisition mode when CS is HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Data Output. The conversion result is provided on DOUT. The serial data output word

7

DOUT

is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion, the

 

 

 

 

 

 

 

 

data is output on the falling edges of SCLK and is valid on the subsequent rising edges.

8

SCLK

Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must be

9

VIO

applied to this input. VIO must be decoupled to GND with a ceramic capacitor value of 0.1

 

 

 

 

 

 

 

 

µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF.

 

 

 

 

 

 

 

 

Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to

10

 

VA

this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in

 

 

 

 

 

 

 

 

parallel with a bulk capacitor value of 1.0 µF to 10 µF.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

2

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