- •FEATURES
- •APPLICATIONS
- •KEY SPECIFICATIONS
- •DESCRIPTION
- •Connection Diagram
- •Block Diagram
- •Absolute Maximum Ratings
- •Operating Ratings
- •Package Thermal Resistance
- •ADC141S626 Converter Electrical Characteristics
- •ADC141S626 Timing Specifications
- •Timing Diagrams
- •Specification Definitions
- •Typical Performance Characteristics
- •Functional Description
- •REFERENCE INPUT (VREF)
- •ANALOG SIGNAL INPUTS
- •Differential Input Operation
- •Single-Ended Input Operation
- •Input Common Mode Voltage
- •SERIAL DIGITAL INTERFACE
- •CS Input
- •SCLK Input
- •Data Output
- •Applications Information
- •POWER CONSUMPTION
- •PCB LAYOUT AND CIRCUIT CONSIDERATIONS
- •APPLICATION CIRCUITS
- •Revision History
ADC141S626
www.ti.com |
SNAS434B –NOVEMBER 2007 –REVISED MARCH 2013 |
ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter
Check for Samples: ADC141S626
FEATURES
•True Differential Inputs
•Guaranteed Performance from 50 kSPS to 250 kSPS
•External Reference
•Zero-Power Track Mode
•Wide Input Common-Mode Voltage Range
•Operating Temperature Range of −40°C to +85°C
•SPI™ /QSPI™ /MICROWIRE/DSP Compatible Serial Interface
APPLICATIONS
DESCRIPTION
The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA. It also features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage.
•Automotive Navigation
•Portable Systems
•Medical Instruments
•Instrumentation and Control Systems
•Motor Control
•Direct Sensor Interface
KEY SPECIFICATIONS
•Conversion Rate: 50 kSPS to 250 kSPS
•INL: ± 0.95 LSB (Max)
•DNL: ± 0.95 LSB (Max)
•SNR: 82 dBc (Max)
•THD: -90 dBc (Typ)
•ENOB: 13.3 Bits(Min)
•Power Consumption:
–200 kSPS, 3V: 2.0 mW (Typ)
–250 kSPS, 5V: 4.8 mW (Typ)
–Power-Down, 3V: 4 µ W (Typ)
–Power-Down, 5V: 13 µ W (Typ)
The serial data output is binary 2's complement and is compatible with several standards, such as SPI™ , QSPI™ , MICROWIRE, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress; thus, ADC141S626 has no latency.
The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VA of 5V while communicating with a 3V controller on the digital side. With a 3V source, the power consumption when operating at 200 kSPS is 2.0 mW. With a 5V source, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition (power-down) mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications.
Operation is guaranteed over the temperature range of −40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead VSSOP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. |
Copyright © 2007–2013, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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ADC141S626
SNAS434B –NOVEMBER 2007 –REVISED MARCH 2013 |
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www.ti.com |
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Connection Diagram |
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VREF |
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VA |
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VIO |
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ADC141S626 8 |
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SCLK |
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GND |
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DOUT |
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CS |
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Block Diagram
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VREF |
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SAR |
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CONTROL |
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SERIAL |
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INTERFACE |
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+IN |
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CDAC |
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S/H |
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-IN |
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COMPARATOR |
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PIN DESCRIPTIONS |
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Pin No. |
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Description |
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Voltage Reference Input. A voltage reference between 1V and VA must be applied to this |
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1 |
VREF |
input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. |
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A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µFcapacitor is |
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recommended for enhanced performance. |
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2 |
+IN |
Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the |
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ADC141S626. |
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3 |
−IN |
Inverting Input. −IN is the negative analog input for the differential signal applied to the |
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ADC141S626. |
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GND |
Ground. GND is the ground reference point for all signals applied to the ADC141S626. |
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5 |
GND |
Ground. GND is the ground reference point for all signals applied to the ADC141S626. |
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Chip Select Bar. |
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must be active LOW during an SPI conversion, which begins on the |
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CS |
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CS |
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falling edge of CS. The ADC141S626 is in acquisition mode when CS is HIGH. |
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Serial Data Output. The conversion result is provided on DOUT. The serial data output word |
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7 |
DOUT |
is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion, the |
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data is output on the falling edges of SCLK and is valid on the subsequent rising edges. |
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8 |
SCLK |
Serial Clock. SCLK is used to control data transfer and serves as the conversion clock. |
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Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must be |
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9 |
VIO |
applied to this input. VIO must be decoupled to GND with a ceramic capacitor value of 0.1 |
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µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF. |
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Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to |
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10 |
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VA |
this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in |
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parallel with a bulk capacitor value of 1.0 µF to 10 µF. |
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
2 |
Submit Documentation Feedback |
Copyright © 2007–2013, Texas Instruments Incorporated |
Product Folder Links: ADC141S626