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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / ADSP-21262.pdf

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ADSP-21262

Timer PWM_OUT Cycle Timing

The timing specification in Table 14 and Figure 12 applies to Timer PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 14. Timer PWM_OUT Timing

Parameter		Min	Max	Unit
Switching Characteristic
tPWMO	Timer Pulse Width Output	2 tCCLK – 1	2(231 – 1) tCCLK	ns

tPWMO

DAI_P20–1 (TIMER)

Figure 12. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The timing specification in Table 15 and Figure 13 applies to Timer WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 15. Timer Width Capture Timing

Parameter		Min	Max	Unit
Timing Requirement
tPWI	Timer Pulse Width	2 tCCLK	2(231 – 1) tCCLK	ns

tPWI

DAI_P20–1 (TIMER)

Figure 13. Timer Width Capture Timing

Rev. B | Page 21 of 48 | August 2005

ADSP-21262

DAI Pin-to-Pin Direct Routing

See Table 16 and Figure 14 for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O).

Table 16. DAI Pin-to-Pin Routing

Parameter		Min	Max	Unit
Timing Requirement
tDPIO	Delay DAI Pin Input Valid to DAI Output Valid	1.5	10	ns

DAI_Pn

DAI_Pm

tDPIO

Figure 14. DAI Pin-to-Pin Direct Routing

Rev. B | Page 22 of 48 | August 2005

ADSP-21262

Precision Clock Generator (Direct Pin Routing)

The timing in Table 17 and Figure 15 is valid only when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other

Table 17. Precision Clock Generator (Direct Pin Routing)

cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P07 – DAI_P20).

Parameter		Min	Max	Unit
Timing Requirements
tPCGIW	Input Clock Pulse Width	20		ns
tSTRIG	PCG Trigger Setup Before Falling Edge of PCG Input Clock	2		ns
tHTRIG	PCG Trigger Hold After Falling Edge of PCG Input Clock	2		ns
Switching Characteristics
tDPCGIO	PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
	Clock Falling Edge	2.5	10	ns
tDTRIG	PCG Output Clock and Frame Sync Delay After PCG Trigger	2.5 + 2.5 × tPCGOW	10 + 2.5 × tPCGOW	ns
tPCGOW	Output Clock Pulse Width	40		ns

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

tSTRIG
tHTRIG	tPCGIW
	tPCGIW
tDPCGIO
	tPCGOW
tDTRIG

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. B | Page 23 of 48 | August 2005

ADSP-21262

Flags

The timing specifications in Table 18 and Figure 16 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 2 on Page 11 for more information on flag use.

Table 18.	Flags

Parameter		Min		Max	Unit
Timing Requirement
tFIPW	FLAG3–0 IN Pulse Width	2	× tCCLK + 3		ns
Switching Characteristic
tFOPW	FLAG3–0 OUT Pulse Width	2	× tCCLK – 1		ns

DAI_P20–1

(FLAG3–0IN) (AD15–0)

tFIPW

DAI_P20–1 (FLAG3–0OUT)

(AD15–0)

tFOPW

Figure 16. Flags

Rev. B | Page 24 of 48 | August 2005

ADSP-21262

Memory Read—Parallel Port

The specifications in Table 19, Table 20, Figure 17, and Figure 18 are for asynchronous interfacing to memories (and

memory-mapped peripherals) when the ADSP-21262 is accessing external memory space.

Table 19. 8-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

tDRS

Address/Data7–0 Setup Before

High

3.3

tDRH

Address/Data7–0 Hold After

High

tDAD

Address 15–8 to Data Valid

D + 0.5 × tCCLK – 3.5

Switching Characteristics

tALEW

ALE Pulse Width

2 × tCCLK – 2

tALERW

ALE Deasserted to Read/Write Asserted

1 × tCCLK – 0.5

tADAS

Address/Data15–0 Setup Before ALE Deasserted1

2.5

× tCCLK –

2.0

tADAH

Address/Data15–0 Hold After ALE Deasserted1

0.5

× tCCLK –

0.8

tALEHZ

ALE Deasserted1 to Address/Data7–0 in High Z

0.5

× tCCLK –

0.8

0.5 × tCCLK + 2.0

tRW

Pulse Width

D – 2

tADRH

Address/Data15–8 Hold After

High

0.5

× tCCLK –

1 + H

D = (data cycle duration) × tCCLK

H = tCCLK (if a hold cycle is specified, else H = 0)

1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

tALEW

tALERW

tRW

tALEHZ

AD15-8

tADAS

tADAH

tADRH

VALID ADDRESS

tDRS

tDRH

AD7-0

VALID ADDRESS

VALID DATA

tDAD

Figure 17. 8-Bit Memory Read Cycle

Rev. B | Page 25 of 48 | August 2005

ADSP-21262

Table 20. 16-Bit Memory Read Cycle

Parameter							Min		Max	Unit
Timing Requirements
tDRS	Address/Data15–0 Setup Before					high	3.3			ns
				RD
tDRH	Address/Data15–0 Hold After				high		0			ns
			RD
Switching Characteristics										ns
tALEW	ALE Pulse Width						2	× tCCLK – 2		ns
tALERW	ALE Deasserted to Read/Write Asserted						1	× tCCLK – 0.5		ns
tADAS	Address/Data15–0 Setup Before ALE Deasserted1						2.5 × tCCLK – 2.0			ns
tADAH	Address/Data15–0 Hold After ALE Deaserted1						0.5 × tCCLK – 0.8			ns
tALEHZ	ALE Deasserted1 to Address/Data15–0 in High Z						0.5 × tCCLK – 0.8		0.5tCCLK + 2.0	ns
tRW		Pulse Width					D – 2			ns
	RD

D = (data cycle duration) × tCCLK

H = tCCLK (if a hold cycle is specified, else H = 0)

1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

tALEW

tALERW

tRW

tADAH

tDRS

tDRH

tADAS

AD15-0

VALID DATA

VALID ADDRESS

tALEHZ

Figure 18. 16-Bit Memory Read Cycle

Rev. B | Page 26 of 48 | August 2005

ADSP-21262

Memory Write—Parallel Port

Use the specifications in Table 21, Table 22, Figure 19, and Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21262 is accessing external memory space.

Table 21. 8-Bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

tALEW

ALE Pulse Width

2 × tCCLK – 2

tALERW

ALE Deasserted to Read/Write Asserted

1 × tCCLK – 0.5

tADAS

Address/Data15–0 Setup Before ALE Deasserted1

2.5

× tCCLK –

2.0

tADAH

Address/Data15–0 Hold After ALE Deasserted1

0.5

× tCCLK –

0.8

tWW

Pulse Width

D – 2

tADWL

Address/Data15–8 to

Low

0.5

× tCCLK –

1.5

tADWH

Address/Data15–8 Hold After

High

0.5

× tCCLK –

1 + H

tALEHZ

ALE Deasserted1 to Address/Data15–0 in High Z

0.5

× tCCLK –

0.8

0.5tCCLK + 2.0

tDWS

Address/Data7–0 Setup Before

High

tDWH

Address/Data7–0 Hold After

High

0.5

× tCCLK –

1.5 + H

tDAWH

Address/Data to

High

D = (data cycle duration) × tCCLK

H = tCCLK (if a hold cycle is specified, else H = 0)

1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

tALERW

ALE

tALEW

RD	tALEHZ

tADAS tADAH

	tDAWH
	tWW
tADWL	tADWH

AD15-8

VALID ADDRESS

tDWS tDWH

AD7-0

VALID ADDRESS

VALID DATA

Figure 19. 8-Bit Memory Write Cycle

Rev. B | Page 27 of 48 | August 2005

ADSP-21262

Table 22. 16-Bit Memory Write Cycle

Parameter							Min			Max	Unit
Switching Characteristics
tALEW	ALE Pulse Width						2 × tCCLK – 2				ns
tALERW	ALE Deasserted to Read/Write Asserted						1 × tCCLK – 0.5				ns
tADAS	Address/Data 15–0 Setup Before ALE Deasserted1						2.5	× tCCLK –	2.0		ns
tADAH	Address/Data15–0 Hold After ALE Deasserted1						0.5	× tCCLK –	0.8		ns
tWW		Pulse Width					D – 2				ns
	WR
tALEHZ	ALE Deasserted1 to Address/Data15–0 in High Z						0.5	× tCCLK –	0.8	0.5tCCLK + 2.0	ns
tDWS	Address/Data15–0 Setup Before					High	D				ns
				WR
tDWH	Address/Data15–0 Hold After				High		0.5	× tCCLK –	1.5 + H		ns
			WR

D = (data cycle duration) × tCCLK

H = tCCLK (if a hold cycle is specified, else H = 0)

1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

tALEW

tALERW

tWW

tALEH

tADAS

tADAH

tDWS

tDWH

AD15-0

VALID ADDRESS

VALID DATA

Figure 20. 16-Bit Memory Write Cycle

Rev. B | Page 28 of 48 | August 2005

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