- •Summary
- •Key Features
- •Additional Key Features
- •Table of Contents
- •Revision History
- •General Description
- •ADSP-21262 Family Core Architecture
- •SIMD Computational Engine
- •Independent, Parallel Computation Units
- •Data Register File
- •Single-Cycle Fetch of Instruction and Four Operands
- •Instruction Cache
- •Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- •Flexible Instruction Set
- •ADSP-21262 Memory and I/O Interface Features
- •Dual-Ported On-Chip Memory
- •DMA Controller
- •Digital Applications Interface (DAI)
- •Serial Ports
- •Serial Peripheral (Compatible) Interface
- •Parallel Port
- •Timers
- •Program Booting
- •Phase-Locked Loop
- •Power Supplies
- •Target Board JTAG Emulator Connector
- •Development Tools
- •Evaluation Kit
- •Designing an Emulator-Compatible DSP Board (Target)
- •Additional Information
- •Pin Function Descriptions
- •Address Data Pins as Flags
- •Boot Modes
- •Core Instruction Rate to CLKIN Ratio Modes
- •Address Data Modes
- •ADSP-21262 Specifications
- •Recommended Operating Conditions
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •ESD Sensitivity
- •Timing Specifications
- •Power-Up Sequencing
- •Clock Input
- •Clock Signals
- •Reset
- •Interrupts
- •Core Timer
- •Timer PWM_OUT Cycle Timing
- •Timer WDTH_CAP Timing
- •DAI Pin-to-Pin Direct Routing
- •Precision Clock Generator (Direct Pin Routing)
- •Flags
- •Serial Ports
- •Input Data Port (IDP)
- •Parallel Data Acquisition Port (PDAP)
- •JTAG Test Access Port and Emulation
- •Output Drive Currents
- •Test Conditions
- •Capacitive Loading
- •Environmental Conditions
- •Thermal Characteristics
- •136-Ball BGA Pin Configurations
- •144-Lead LQFP Pin Configurations
- •Package Dimensions
- •Ordering Guide
ADSP-21262
PACKAGE DIMENSIONS
The ADSP-21262 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 and Figure 36.
12.00 BSC SQ |
0.80 |
10.40 BSC SQ |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
||
|
BSC |
|
|
|
|
|
|
|
|
|
|
TYP A |
|
|
|
|
|
|
|
|
|
PIN A1 INDICATOR |
B |
|
|
|
|
|
|
|
|
|
|
C |
|
|
|
|
|
|
|
|
|
|
D |
|
|
|
|
|
|
|
|
|
|
E |
|
|
|
|
|
|
|
|
|
|
F |
|
|
|
|
|
|
|
|
|
|
G |
|
|
|
|
|
|
|
|
|
|
H |
|
|
|
|
|
|
|
|
|
|
J |
|
|
|
|
|
|
|
|
|
|
K |
|
|
|
|
|
|
|
|
0.80 |
|
L |
|
|
|
|
|
|
|
|
BSC |
|
M |
|
|
|
|
|
|
|
|
TYP |
|
N |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
|
|
|
|
|
|
|
|
|
TOP VIEW |
|
14 13 12 11 10 9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
|
|
|
|
|
|
|
|
|
|
|
1.70 |
DETAIL A |
BOTTOM VIEW |
|
|
|
|
||||
MAX |
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
1. |
DIMENSIONS ARE IN MILIMETERS (MM). |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2. |
THE ACTUAL POSITION OF THE BALL GRID IS |
0.25 |
|
|
0.50 |
|
|
|
|
|
|
|
|
|
SEATING |
|
|
WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE |
MIN |
|
0.45 |
|
|
|
|
|
|
|
|
|
PLANE |
||
|
TO THE PACKAGE EDGES. |
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
0.40 |
|
|
|
|
|
|
|
0.12 MAX (BALL |
|||||
3. |
COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR |
|
|
|
|
|
|
|
|
|
||||||
|
|
|
(BALL |
|
|
|
COPLANARITY) |
|||||||||
|
THE BALL DIAMETER. |
|
|
|
|
|
|
|||||||||
4. |
CENTER DIMENSIONS ARE NOMINAL. |
|
|
|
DIAMETER) |
|
|
|
|
|
|
DETAIL A
Figure 35. 136-Ball BGA (BC-136-3)
|
|
|
22.00 BSC SQ |
|
|
|
|
20.00 BSC SQ |
|
|
|
144 |
109 |
|
|
|
1 |
108 |
|
|
|
|
PIN 1 INDICATOR |
|
0.27 |
|
0.50 |
|
|
0.22 TYP |
|
BSC |
|
|
0.17 |
|
TYP |
|
|
|
(LEAD |
|
||
|
|
|
||
|
|
PITCH) |
|
|
SEATING |
|
|
|
|
PLANE |
|
|
|
|
0.08 MAX (LEAD |
|
|
|
|
COPLANARITY) |
|
|
|
|
0.15 |
|
|
|
|
0.05 |
|
|
|
|
0.75 |
1.45 |
|
|
|
1.40 |
|
|
||
0.60 TYP |
|
73 |
||
1.35 |
3 6 |
|||
0.45 |
||||
|
37 |
72 |
||
|
1.60 MAX |
|||
|
|
|
||
|
|
DETAIL A |
||
|
DETAIL A |
|
TOP VIEW (PINS DOWN) |
1.DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB.
2.ACTUAL POSITION OF EACH LEAD
IS WITHIN 0.08 OF ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
3.CENTER DIMENSIONS ARE NOMINAL.
Figure 36. 144-Lead LQFP (ST-144-2)
Rev. B | Page 45 of 48 | August 2005
ADSP-21262
ORDERING GUIDE
|
Temperature |
Instruction |
On-Chip |
|
Operating |
Package |
Package |
Model |
Range1 |
Rate |
SRAM |
ROM |
Voltage |
Description |
Option |
ADSP-21262SKBC-200 |
0°C to +70°C |
200 MHz |
2M bit |
4M bit |
1.2 INT/3.3 EXT V |
136-Lead BGA |
BC-136-3 |
ADSP-21262SKBCZ2002 |
0°C to +70°C |
200 MHz |
2M bit |
4M bit |
1.2 INT/3.3 EXT V |
136-Lead BGA |
BC-136-3 |
ADSP-21262SKSTZ2002 |
0°C to +70°C |
200 MHz |
2M bit |
4M bit |
1.2 INT/3.3 EXT V |
144-Lead LQFP |
ST-144-2 |
ADSP-21262SBBC-150 |
–40°C to +85°C |
150 MHz |
2M bit |
4M bit |
1.2 INT/3.3 EXT V |
136-Lead BGA |
BC-136-3 |
ADSP-21262SBBCZ1502 |
–40°C to +85°C |
150 MHz |
2M bit |
4M bit |
1.2 INT/3.3 EXT V |
136-Lead BGA |
BC-136-3 |
1 Ranges shown represent ambient temperature.
2 Z=Pb-free part.
Rev. B | Page 46 of 48 | September 2005
ADSP-21262
Rev. B | Page 47 of 48 | August 2005
ADSP-21262
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D04442-0-8/05(B)
Rev. B | Page 48 of 48 | August 2005