ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port.

Table 3. AD15–0 to FLAG Pin Mapping

Boot Modes

Table 4. Boot Mode Selection

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 5. Core Instruction Rate/CLKIN Ratio Selection

ADDRESS DATA MODES

Table 6 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15–A0 when asserted, followed by data bits D15–D0 when deasserted.

Table 6. Address/Data Mode Selection