- •Features
- •Memory
- •Peripherals
- •Table Of Contents
- •Revision History
- •General Description
- •Portable Low Power Architecture
- •System Integration
- •ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor Peripherals
- •Blackfin Processor Core
- •Memory Architecture
- •Internal (On-Chip) Memory
- •External (Off-Chip) Memory
- •I/O Memory Space
- •Booting
- •Event Handling
- •Core Event Controller (CEC)
- •System Interrupt Controller (SIC)
- •Event Control
- •DMA Controllers
- •Real-Time Clock
- •Watchdog Timer
- •Timers
- •Serial Ports (SPORTs)
- •Serial Peripheral Interface (SPI) Port
- •UART Port
- •General-Purpose I/O Port F
- •Parallel Peripheral Interface
- •General-Purpose Mode Descriptions
- •Input Mode
- •Frame Capture Mode
- •Output Mode
- •ITU-R 656 Mode Descriptions
- •Active Video Only Mode
- •Vertical Blanking Interval Mode
- •Entire Field Mode
- •Dynamic Power Management
- •Power Savings
- •Voltage Regulation
- •Voltage Regulator Layout Guidelines
- •Clock Signals
- •Booting Modes
- •Instruction Set Description
- •Development Tools
- •EZ-KIT Lite Evaluation Board
- •Designing an Emulator-Compatible Processor Board
- •Related Documents
- •Pin Descriptions
- •Specifications
- •Operating Conditions
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •Package Information
- •ESD Sensitivity
- •Timing Specifications
- •Clock and Reset Timing
- •Asynchronous Memory Read Cycle Timing
- •Asynchronous Memory Write Cycle Timing
- •SDRAM Interface Timing
- •External Port Bus Request and Grant Cycle Timing
- •Parallel Peripheral Interface Timing
- •Serial Ports
- •General-Purpose I/O Port F Pin Cycle Timing
- •Timer Cycle Timing
- •JTAG Test and Emulation Port Timing
- •Output Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Enable Time Measurement
- •Output Disable Time Measurement
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Environmental Conditions
- •160-Ball BGA Ball Assignment
- •169-Ball PBGA ball assignment
- •176-Lead LQFP Pinout
- •Outline Dimensions
- •Surface Mount Design
- •Ordering Guide
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTLINE DIMENSIONS
Dimensions in the outline dimension figures are shown in millimeters.
0.75 |
26.00 BSC SQ |
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0.60 |
24.00 BSC SQ |
0.45 |
133 |
176 |
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1 |
132 |
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PIN 1 |
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX LEAD COPLANARITY
0.15 |
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0.05 |
1.45 |
44 |
89 |
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1.40 |
45 |
88 |
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1.35 |
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1.60 MAX |
DETAIL A |
0.50 BSC |
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LEAD PITCH |
DETAIL A
TOP VIEW (PINS DOWN)
NOTES
1.DIMENSIONS IN MILLIMETERS
2.ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL
Figure 61. 176-Lead Low Profile Quad Flat Package (LQFP) ST-176-1
12.00 BSC SQ |
12 |
10 |
8 |
6 |
4 |
2 |
A1 CORNER |
14 |
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13 |
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11 9 |
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7 |
5 |
3 1 |
INDEX AREA |
BALL A1 |
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A |
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B |
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INDICATOR |
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C |
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D |
10.40 |
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E |
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F |
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BSC |
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G |
SQ |
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H |
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J |
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K |
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L |
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M |
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N |
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P |
TOP VIEW |
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0.80 BSC |
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BALL PITCH |
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1.31 |
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1.21 |
1.70 |
DETAIL A |
1.11 |
MAX |
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SEATING |
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PLANE |
0.40 NOM |
(NOTE 3)
NOTES
1.DIMENSIONS ARE IN MILLIMETERS.
2.COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION AE WITH EXCEPTION OF
THE BALL DIAMETER.
3. MINIMUM BALL HEIGHT 0.25.
BOTTOM VIEW
0.50 |
0.12 |
0.45 |
MAX |
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COPLANARITY |
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0.40 |
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BALL DIAMETER |
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DETAIL A
Figure 62. 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2
Rev. E | Page 57 of 60 | July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 BALL PAD CORNER
19.00 BSC SQ 
TOP VIEW
2.50 |
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SIDE VIEW |
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2.23 |
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1.97 |
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DETAIL A
NOTES
1.DIMENSIONS ARE IN MILLIMETERS.
2.COMPLIES WITH JEDEC REGISTERED OUTLINE
MS-034, VARIATION AAG-2 |
. |
3. MINIMUM BALL HEIGHT 0.40 |
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16.00 BSC SQ 
1.00 BSC
BALL PITCH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
16 |
14 |
12 |
10 |
8 |
6 |
4 |
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2 |
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17 |
15 |
13 |
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11 |
9 |
7 |
5 |
3 |
1 |
BOTTOM VIEW
0.40 MIN
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0.20 MAX |
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COPLANARITY |
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SEATING PLANE |
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0.70 |
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DETAIL A |
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BALL DIAMETER 0.60 |
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0.50 |
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Figure 63. 169-Ball Plastic Ball Grid Array (B-169)
SURFACE MOUNT DESIGN
Table 40 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat tern Standard.
Table 40. BGA Data for Use with Surface Mount Design
Package |
Ball Attach Type |
Solder Mask Opening |
Ball Pad Size |
Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2 |
Solder Mask Defined |
0.40 mm diameter |
0.55 mm diameter |
Plastic Ball Grid Array (PBGA) B-169 |
Solder Mask Defined |
0.43 mm diameter |
0.56 mm diameter |
Rev. E | Page 58 of 60 | July 2007
